arm-trusted-firmware

Commit Graph

Author	SHA1	Message	Date
Madhukar Pappireddy	83e955241a	Workaround for Hercules erratum 1688305 Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions of Hercules core. The erratum can be avoided by setting bit 1 of the implementation defined register CPUACTLR2_EL1 to 1 to prevent store- release from being dispatched before it is the oldest. Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>	2019-12-23 11:21:16 -06:00
Balint Dobszay	3d08461a2d	Enable AMU for Cortex-Hercules Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>	2019-07-31 15:04:03 +00:00
Louis Mayencourt	294f9ef9f9	Cortex_hercules: Introduce preliminary cpu support Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>	2019-07-16 16:36:51 +01:00

Author

SHA1

Message

Date

Madhukar Pappireddy

83e955241a

Workaround for Hercules erratum 1688305

Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.

Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

2019-12-23 11:21:16 -06:00

Balint Dobszay

3d08461a2d

Enable AMU for Cortex-Hercules

Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

2019-07-31 15:04:03 +00:00

Louis Mayencourt

294f9ef9f9

Cortex_hercules: Introduce preliminary cpu support

Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

2019-07-16 16:36:51 +01:00

3 Commits