Commit Graph

6619 Commits

Author SHA1 Message Date
Mark Dykes 235c8174ff Merge "Coverity: remove unnecessary header file includes" into integration 2020-02-04 17:15:57 +00:00
Sandrine Bailleux 9eac8e958e Merge changes from topic "mp/separate_nobits" into integration
* changes:
  plat/arm: Add support for SEPARATE_NOBITS_REGION
  Changes necessary to support SEPARATE_NOBITS_REGION feature
2020-02-04 16:37:09 +00:00
Zelalem e6937287e4 Coverity: remove unnecessary header file includes
This patch removes unnecessary header file includes
discovered by Coverity HFA option.

Change-Id: I2827c37c1c24866c87db0e206e681900545925d4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
2020-02-04 10:23:51 -06:00
Soby Mathew 44e3424e34 Merge "coverity: debugfs devfip remove comparisons to LONG_MAX" into integration 2020-02-04 15:03:59 +00:00
Manish Pandey d57a582a5b Merge "intel: agilex: Enable uboot BL31 loading" into integration 2020-02-04 13:42:36 +00:00
Olivier Deprez 47939f6725 coverity: debugfs devfip remove comparisons to LONG_MAX
CID 353228:  Integer handling issues  (CONSTANT_EXPRESSION_RESULT)

The checks on size and offset_address in get_entry always resolve to
false provided those fields are long long int and cannot be greater
than LONG_MAX.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I0fac485a39ac4a40ae8c0d25a706ad74c795e130
2020-02-04 13:40:30 +00:00
Sandrine Bailleux 4ad18e5df3 Merge "BL2: Print ID of images we fail loading" into integration 2020-02-04 08:27:06 +00:00
Sandrine Bailleux a416325bc1 BL2: Print ID of images we fail loading
When Trusted Boot is enabled, images are loaded and authenticated
following up the root of trust. This means that between the initial
console message saying that an image is being loaded, and the final one
where it says that it failed to load it, BL2 may print several messages
about other images on the chain of trust being loaded, thus it is not
always clear which image we failed loading at the end of the day.

Change-Id: I3b189ec9d12c2a6203d16c8dbbb4fc117639c3c1
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-02-03 16:11:56 +01:00
Manish Pandey 5f62213e68 Merge "FDT wrappers: add functions for read/write bytes" into integration 2020-02-03 13:45:47 +00:00
Alexei Fedorov 0a2ab6e635 FDT wrappers: add functions for read/write bytes
This patch adds 'fdtw_read_bytes' and 'fdtw_write_inplace_bytes'
functions for read/write array of bytes from/to a given property.
It also adds 'fdt_setprop_inplace_namelen_partial' to jmptbl.i
files for builds with USE_ROMLIB=1 option.

Change-Id: Ied7b5c8b38a0e21d508aa7bcf5893e656028b14d
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-02-03 11:41:27 +00:00
Sandrine Bailleux 9db293d1f1 Merge "doc: qemu: fix and update documentation" into integration 2020-02-03 09:20:29 +00:00
Masahiro Yamada 62038be731 doc: qemu: fix and update documentation
The current URL for QEMU_EFI.fd is not found. Update the link to
point to the new one.

If you run the shell command as instructed, you will see this error:
  qemu-system-aarch64: keep_bootcon: Could not open 'keep_bootcon': No such file or directory

The part "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2" is the
kernel parameter, so it must be quoted.

As of writing, QEMU v4.2.0 is the latest, but it does not work for
TF-A (It has been fixed in the mainline.) QEMU v4.1.0 works fine.

With those issues addressed, I succeeded in booting the latest kernel.

Tested with QEMU v4.1.0 and Linux 5.5 (defconfig with no modification).
Update the tested versions.

Change-Id: Ic85db0e688d67b1803ff890047d37de3f3db2daa
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-03 18:10:45 +09:00
Sandrine Bailleux 989429e872 Merge "Add support for documentation build as a target in Makefile" into integration 2020-01-31 07:35:30 +00:00
Alexei Fedorov f69a5828b7 Merge "Use correct type when reading SCR register" into integration 2020-01-30 16:55:55 +00:00
Sandrine Bailleux b7e0ed2c71 Merge "Ignore the ctags file" into integration 2020-01-30 14:47:07 +00:00
Sandrine Bailleux dcd03ce7bb Merge changes from topic "sb/select-cot" into integration
* changes:
  Introduce COT build option
  cert_create: Remove references to TBBR in common code
  cert_create: Introduce COT build option
  cert_create: Introduce TBBR CoT makefile
2020-01-30 13:58:10 +00:00
Soby Mathew b1d810bd21 Merge "qemu: Implement PSCI_CPU_OFF." into integration 2020-01-29 15:36:30 +00:00
Soby Mathew 458dde3c44 Merge "T589: Fix insufficient ordering guarantees in bakery lock" into integration 2020-01-29 15:35:23 +00:00
Sandrine Bailleux 3bff910dc1 Introduce COT build option
Allows to select the chain of trust to use when the Trusted Boot feature
is enabled. This affects both the cert_create tool and the firmware
itself.

Right now, the only available CoT is TBBR.

Change-Id: I7ab54e66508a1416cb3fcd3dfb0f055696763b3d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-01-29 14:00:33 +01:00
Sandrine Bailleux 067f7e9c52 cert_create: Remove references to TBBR in common code
In preparation of supporting alternate chains of trust, reword comments
and error messages that explicitly mentioned TBBR.

Change-Id: I85a0b08e16d0cd82f3b767fcc092d1f20f45939f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-01-29 14:00:32 +01:00
Sandrine Bailleux 43743ea57d cert_create: Introduce COT build option
It allows to select the desired chain of trust. Right now, only the TBBR
CoT is available.

At this stage, this build option only affects the tool itself. It is not
plugged into the rest of the build system yet. To use it:

 > make -C tools/cert_create COT=tbbr

Change-Id: I4484418f76d3c7b330d8653c978499a181534dcd
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-01-29 14:00:32 +01:00
Sandrine Bailleux 3b24b66edc cert_create: Introduce TBBR CoT makefile
Move all TBBR-specific stuff out of the tool's makefile into a
sub-makefile. This will make it easier to define and select an alternate
chain of trust in the future.

Change-Id: I92e366a1999b74cf51127d1771b64b807cd94b29
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-01-29 14:00:14 +01:00
Madhukar Pappireddy 6de32378f6 Add support for documentation build as a target in Makefile
Command to build HTML-formatted pages from docs:
make doc

Change-Id: I4103c804b3564fe67d8fc5a3373679daabf3f2e9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-29 06:26:09 -06:00
Andrew Walbran 33e8c56973 qemu: Implement PSCI_CPU_OFF.
This is based on the rpi implementation from
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1
2020-01-29 10:50:25 +00:00
Soby Mathew 8efec9e097 Merge changes I0fb7cf79,Ia8eb4710 into integration
* changes:
  qemu: Implement qemu_system_off via semihosting.
  qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
2020-01-29 09:51:21 +00:00
Soby Mathew c1f118f1a7 Merge "Enable -Wredundant-decls warning check" into integration 2020-01-29 09:50:05 +00:00
Hadi Asyrafi 2a1e086677 intel: agilex: Enable uboot BL31 loading
This patch enables uboot's spl entrypoint to BL31 and also handles
secondary cpus state during cold boot.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c
2020-01-29 12:49:50 +08:00
Mark Dykes b012454d82 Merge "Measured Boot: add function for hash calculation" into integration 2020-01-28 19:57:51 +00:00
Madhukar Pappireddy ca661a0092 Enable -Wredundant-decls warning check
This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-28 11:09:02 -06:00
Alexei Fedorov 8c105290f3 Measured Boot: add function for hash calculation
This patch adds 'calc_hash' function using Mbed TLS library
required for Measured Boot support.

Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-01-28 16:51:40 +00:00
Louis Mayencourt f1be00da0b Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-01-28 11:10:48 +00:00
Soby Mathew 29763ac260 Merge changes from topic "ti-cluster-power" into integration
* changes:
  ti: k3: drivers: ti_sci: Put sequence number in coherent memory
  ti: k3: drivers: ti_sci: Remove indirect structure of const data
  ti: k3: common: Enable ARM cluster power down
  ti: k3: common: Rename device IDs to be more consistent
2020-01-28 10:43:36 +00:00
Manish Pandey 7cd731bc14 Merge "plat/arm/sgi: move topology information to board folder" into integration 2020-01-28 10:26:55 +00:00
Sandrine Bailleux 990185819b Merge "Tegra194: enable spe-console functionality" into integration 2020-01-28 09:43:23 +00:00
Varun Wadekar ffd58cca83 Tegra194: enable spe-console functionality
This patch enables the config to switch to the console provided
by the SPE firmware.

Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-28 09:43:10 +00:00
Manish Pandey 91ff490d75 Merge "Neovers N1: added support to update presence of External LLC" into integration 2020-01-28 08:18:56 +00:00
Madhukar Pappireddy 0c1f197aa1 plat/arm: Add support for SEPARATE_NOBITS_REGION
In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
the build to require that ARM_BL31_IN_DRAM is enabled as well.

Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code
cannot be reclaimed to be used for runtime data such as secondary cpu stacks.

Memory map for BL31 NOBITS region also has to be created.

Change-Id: Ibbc8c9499a32e63fd0957a6e254608fbf6fa90c9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-27 15:38:43 -06:00
Madhukar Pappireddy c367b75e85 Changes necessary to support SEPARATE_NOBITS_REGION feature
Since BL31 PROGBITS and BL31 NOBITS sections are going to be
in non-adjacent memory regions, potentially far from each other,
some fixes are needed to support it completely.

1. adr instruction only allows computing the effective address
of a location only within 1MB range of the PC. However, adrp
instruction together with an add permits position independent
address of any location with 4GB range of PC.

2. Since BL31 _RW_END_ marks the end of BL31 image, care must be
taken that it is aligned to page size since we map this memory
region in BL31 using xlat_v2 lib utils which mandate alignment of
image size to page granularity.

Change-Id: I3451cc030d03cb2032db3cc088f0c0e2c84bffda
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-27 15:33:24 -06:00
Andrew F. Davis 32967a379c ti: k3: drivers: ti_sci: Put sequence number in coherent memory
The current message sequence number is accessed both with caches on and
off so put this memory in the un-cached coherent section so accesses
are consistent and coherency is maintained.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ieeefefeaffc691e4e4c4de7c74490d50ff9de807
2020-01-27 13:26:01 -05:00
Andrew F. Davis 592ede258d ti: k3: drivers: ti_sci: Remove indirect structure of const data
The 'info' structure contained what is only static data for this
implementation of TI-SCI. Remove this indirection and remove the
struct.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I2328fddf388bf7d56a56bd673c080e78c86fe072
2020-01-27 13:26:01 -05:00
Andrew F. Davis 586621f110 ti: k3: common: Enable ARM cluster power down
When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sending the cluster power down sequence to the system
power controller firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I0ffeb339852c66ef62743aecd3e17ca20bad6216
2020-01-27 13:26:01 -05:00
Andrew F. Davis 9f49a177c6 ti: k3: common: Rename device IDs to be more consistent
The core number is called 'core_id' but the processor and device IDs are
called 'proc' and 'device'. Rename these to make them less confusing.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I3d7c6dddd7aa37b5dee1aa9689ce31730e9c3b59
2020-01-27 13:26:01 -05:00
Raghu Krishnamurthy c0018913b4 T589: Fix insufficient ordering guarantees in bakery lock
bakery_lock_get() uses DMB LD after lock acquisition and
bakery_lock_release() uses DMB ST before releasing the lock. This is
insufficient in both cases. With just DMB LD, stores in the critical
section can be reordered before the DMB LD which could mean writes in
the critical section completing before the lock has been acquired
successfully. Similarly, with just DMB ST, a load in the critical section
could be reordered after the the DMB ST. DMB is the least expensive
barrier that can provide the required ordering.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
Change-Id: Ieb74cbf5b76b09e1789331b71f37f7c660221b0e
2020-01-27 09:31:31 -08:00
Soby Mathew 0281e60c3d Merge changes from topic "pie" into integration
* changes:
  uniphier: make all BL images completely position-independent
  uniphier: make uniphier_mmap_setup() work with PIE
  uniphier: pass SCP base address as a function parameter
  uniphier: set buffer offset and length for io_block dynamically
  uniphier: use more mmap_add_dynamic_region() for loading images
  bl_common: add BL_END macro
  uniphier: turn on ENABLE_PIE
  TSP: add PIE support
  BL2_AT_EL3: add PIE support
  BL31: discard .dynsym .dynstr .hash sections to make ENABLE_PIE work
  PIE: pass PIE options only to BL31
  Build: support per-BL LDFLAGS
2020-01-27 17:01:07 +00:00
Manish Pandey f2d6b4ee57 Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.

To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
2020-01-27 14:44:35 +00:00
Vijayenthiran Subramaniam a9fbf13e04 plat/arm/sgi: move topology information to board folder
The platform topology description of the upcoming Arm's RD platforms
have different topology than those listed in the sgi_topology.c file. So
instead of adding platform specific topology into existing
sgi_topology.c file, those can be added to respective board files. In
order to maintain consistency with the upcoming platforms, move the
existing platform topology description to respective board files.

Change-Id: I4689c7d24cd0c75a3dc234370c34a85c08598abb
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2020-01-27 19:54:05 +05:30
Manish Pandey 432e9ee243 Merge "plat/sgm: Always use SCMI for SGM platforms" into integration 2020-01-27 13:05:54 +00:00
Mark Dykes 9054018bd5 Merge "xilinx: Unify Platform specific defines for PSCI module" into integration 2020-01-24 17:03:17 +00:00
Chris Kay f2aa4e882b plat/sgm: Always use SCMI for SGM platforms
As on SGI platforms, SCPI is unsupported on SGM platforms.

Change-Id: I556ed095b9eb55b72447230ee2725d3c76160a08
Signed-off-by: Chris Kay <chris.kay@arm.com>
2020-01-24 16:33:12 +00:00
Deepika Bhavnani 6cdef9ba11 xilinx: Unify Platform specific defines for PSCI module
PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I76f5535f1cbdaf3fc1235cd824111d9afe8f7e1b
2020-01-24 10:02:15 -06:00