Implement below pin control related APIs:
- Request pin
- Release pin
- Set pin function
- Get pin function
- Set pin parameter value
- Get pin parameter value
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ib805cc8c936b63206d44bf1f7bebd0f03f7b3c01
Add support for EEMI API get_api_verion.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic1ef90a194ae6164994a7fc5d8ff0b7b192636fe
Port ZynqMP PM services for versal to send PM APIs to PMC
using IPI.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I27a52faf27f1a2919213498276a6885a177cb6da
Move versal_def.h to platform specific include directory.
Also, update source file to include header file from updated
path of versal_def.h
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I313592a17552843b9cc7048f31bcaaefa40ffd91
Move versal_private.h to platform specific include directory.
Also, rename it to plat_private.h instead of having platform
name. So, it can be used to common source files which needs
platform specific data.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I65eefbea7722ffa2760b992491c00eebef5bcef4
- Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts
to be targeted to EL3.
- Raise SGI interrupts for individual CPU cores as GIC API
uses CPU num as parameter, not CPU mask.
- Flag WARMBOOT_ENABLE_DCACHE_EARLY needs to be set to enable
CPU interface mask work properly for all CPU cores which is
required when generating SGI.
- Call plat_ic_end_of_interrupt() from ttc_fiq_handler() to clear
GIC interrupt to avoid same interrupt again.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I71d4935b8d4688a3729c62753ca8a1a77cd92ae7
This patch adds support for CRC checksum for IPI data when the
macro ZYNQMP_IPI_CRC_CHECK is defined.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic981f162666b3c1fffeb1b9fef3ee7714ecd889d
UEFI decompression will fail if the payload size is too large and the load
address is too low. This patch moves the payload to a higher address to fix
the issue
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396
All function in socfpga_sip_svc.c should only be called locally except
sip_smc_handler().
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib84ef9a2e521967baa4cfd32e6bc569dd3a5d2f5
Now that there is plenty of space (32 KiB) available for NOBITS
sections, we can afford using an entire page for coherent memory. In
fact, because it simplifies the code, this is a beneficial change for
loaded image (.text) size, where we are still close to the size limit.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9
Implements a way to add platform specific power off code to a
Marvell Armada 8K platform.
Marvell Armada 8K boards can now add a board/system_power.c file
that contains a system_power_off() function.
This function can now send a command to a power management MCU or
other board periferals before shutting the board down.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: Iaba20bc2f603195679c54ad12c0c18962dd8e3db
---
I am working on a device that will be ported later, which has a
custom power management MCU that handles LEDs, board power and fans
and requires this separation.
Add missing #address-cells and #size-cells into generated DT, otherwise
the DT is invalid. While the parsers thus far handled this correctly via
various fallbacks, this is not applicable in the long run, so fix this.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ic808a3b27b93e5258ec1a19acc3d593e53625c15
Add new QID to get maximum supported divisor by clock.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I35fc92457e522f3f0614d983c21e55c2b0b8e80a
Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value to be fixed and only value of DIV2 will be
adjusted according to required clock rate.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b
Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78
Add support to add extra custom type flags and provide
to caller in topology query.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id9cc065dbadfed2291dd4f62674d7838da4cdf40
Add GET_CALLBACK_DATA function again as now Linux driver
supports both mailbox as well as ISR method.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ieb99d61976e1cb718fcd1021d9cf4958e7556c81
It's in fact mandatory. Seen with RPi firmware 1.20190925.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I80739b74f25817294adc52cfd26a3ec59c06f892
The chain of trust definitions are only needed in the part of the code
dealing with the TBBR CoT (tbbr/* files).
Change-Id: I6f9a86bba4a2d16313b6842a3ec85b7c951074bc
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* changes:
zynqmp: pm: Add LPD WDT clock to the pm_clock structure
zynqmp: pm: Fix clock models and IDs of GEM-related clocks
zynqmp: pm: Rename FPD WDT clock ID
plat: xilinx: zynqmp: Correct syscnt freq for QEMU
arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
arm64: zynqmp: Add id for new RFSoC device ZU39DR
Using the /include/ syntax, the include was evaluated by dtc, only after running
the preprocessor, therefore the .dtsi files were not preprocessed. This patch
adds the #include syntax instead. Evaluating this and preprocessing the files
now happens in a single step, done by the C preprocessor.
Change-Id: I6d0104b6274316fc736e84973502a4d6c2c9d6e0
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
This patch removes un-needed r/w parameter checks for qspi driver. The
driver can actually access any offset and size.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If60b2c016aa91e2c24ddc57c6ad410c8dc5dcf53
This patch fixes the violations of Rule 21.1 from all the
header files.
Rule 21.1 "#define and #undef shall not be used on a reserved
identifier or reserved macro name"
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I12e17a5d7158defd33b03416daab3049749905fc
This patch fixes the violations of Rule 21.1 from all the
Tegra common header files.
Rule 21.1 "#define and #undef shall not be used on a reserved
identifier or reserved macro name"
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185
This toolchain provides multiple cross compilers and are publicly
available on developer.arm.com
We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)
Change-Id: I910200174d5bad985504d1af4a1ae5819b524003
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
IO seek offset can be set to values above UINT32_MAX, this change
changes the seek offset argument from 'ssize_t' to 'signed long long'.
Fixing platform seek functions to match the new interface update.
Change-Id: I25de83b3b7abe5f52a7b0fee36f71e60cac9cfcb
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned int" type.
Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.
2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent
Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.
Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
Tejas Patel
Siva Durga Prasad Paladugu
Venkatesh Yadav Abbarapu
Manish Pandey
Tien Hock, Loh
Hadi Asyrafi
Alexei Fedorov
Samuel Holland
Luka Kovacic
Marek Vasut
Rajan Vaja
Ravi Patel
Olivier Deprez
Jan Kiszka
Sandrine Bailleux
Balint Dobszay
Varun Wadekar
Madhukar Pappireddy
Yann Gautier
Mark Dykes
Deepika Bhavnani