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6 Commits

Author SHA1 Message Date
Sumit Garg 5931fdac63 synquacer: Enable System level Generic timer 
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
 2018-06-21 11:22:57 +05:30
Sumit Garg b529799ff1 synquacer: Enable GICv3 support 
synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver
initialization.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
 2018-06-21 11:22:52 +05:30
Sumit Garg 0eb275c9a2 synquacer: Enable CCN driver support 
synquacer has CCN-512 interconnect. So enable proper CCN driver
initialization.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
 2018-06-21 11:22:48 +05:30
Sumit Garg 5e5cfc21f0 synquacer: Populate BL32 and BL33 entrypoints 
As this platform supports direct entry to BL31 and no BL2, so
populate BL32 and BL33 entrypoints with static memory load info.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
 2018-06-21 11:22:36 +05:30
Sumit Garg 67b400705f synquacer: Enable PL011 UART Console 
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
 2018-06-21 11:22:32 +05:30
Sumit Garg c35d59a3d8 synquacer: Introduce basic platform support 
synquacer supports direct entry to BL31 without BL1 and BL2 as
SCP firmware does similar work. So this patch adds BL31 stub APIs.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
 2018-06-21 11:22:23 +05:30