Commit Graph

4186 Commits

Author SHA1 Message Date
Konstantin Porotchkin 6414dc6d97 tools: Move doimage to marvell folder for future add-ons
Move doimage utility from toos/doimage to tools/marvell/doimage.
This is done for supporting mode Marvell tools in the future.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-10-22 18:17:52 +03:00
Grzegorz Jaszczyk 42a293379e mvebu: cp110: introduce COMPHY porting layer
Some of COMPHY parameters depends on the hw connection between the SoC
and the PHY, which can vary on different boards e.g. due to different
wires length. Define the "porting layer" with some defaults
parameters. It ease updating static values which needs to be updated due
to board differences, which are now grouped in one place.

Example porting layer for a8k-db is under:
plat/marvell/a8k/a80x0/board/phy-porting-layer.h

If for some boards parameters are not defined (missing
phy-porting-layer.h), the default values are used
(drivers/marvell/comphy/phy-default-porting-layer.h)
and the following compilation warning is show:
"Using default comphy params - you may need to suit them to your board".

The common COMPHY driver code is extracted in order to be shared with
future COMPHY driver for A3700 SoC platforms

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-10-18 12:13:11 +03:00
Konstantin Porotchkin 2b2c3f0a22 plat: marvell: Fix the wrong include protector
Fix the include protector to be in sync with file name

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-10-18 12:13:11 +03:00
Konstantin Porotchkin d90256a7fd lib/mmio: Add mmio_clrsetbits_16 inline function
Add 16-bit variant of mmio_clrsetbits function

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-10-18 12:13:11 +03:00
Soby Mathew a51443fa7e
Merge pull request #1582 from ldts/rcar_gen3/upstream
rcar_gen3: initial support
2018-10-18 09:54:55 +01:00
Soby Mathew 0059be2d95
Merge pull request #1553 from glneo/dcache-late-disable
Allow D-Cache to remain on during core power-down
2018-10-18 09:49:03 +01:00
Soby Mathew 97f12332ff
Merge pull request #1629 from robertovargas-arm/hw-assisted-coherency-lock
Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled
2018-10-18 09:35:14 +01:00
Soby Mathew 1278f363d3
Merge pull request #1631 from deepan02/deepak-arm/relocate-jump_if_cpu_midr
plat/arm: relocate the jump_if_cpu_midr macro.
2018-10-18 09:34:20 +01:00
Soby Mathew 7be05cd5d2
Merge pull request #1628 from antonio-nino-diaz-arm/an/sharing
plat/arm: Small reorganization of platform code
2018-10-18 09:20:04 +01:00
Jorge Ramirez-Ortiz 84433c5096 rcar_gen3: drivers: watchdog
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:42:31 +02:00
Jorge Ramirez-Ortiz 33947f2e4f rcar_gen3: drivers: serial controller interface
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:42:17 +02:00
Jorge Ramirez-Ortiz b3bd0731fd rcar_gen3: drivers: spi multio bus controller
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:42:03 +02:00
Jorge Ramirez-Ortiz 0709efbef5 rcar_gen3: drivers: rom api
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:42:00 +02:00
Jorge Ramirez-Ortiz 32c70e4046 rcar_gen3: drivers: power controller
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:41:57 +02:00
Jorge Ramirez-Ortiz 0a106e2869 rcar_gen3: drivers: console
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:41:53 +02:00
Jorge Ramirez-Ortiz c2f2868204 rcar_gen3: drivers: io [emmc/mem]
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:41:49 +02:00
Jorge Ramirez-Ortiz da963e3164 rcar_gen3: drivers: i2c dvfs
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:41:34 +02:00
Jorge Ramirez-Ortiz 3bfe202af6 rcar_gen3: drivers: emmc
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:41:17 +02:00
Jorge Ramirez-Ortiz 2f7de7271f rcar_gen3: drivers: dma
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:41:13 +02:00
Jorge Ramirez-Ortiz d427fc9711 rcar_gen3: drivers: micro delay generator
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:40:56 +02:00
Jorge Ramirez-Ortiz 3a81abb607 rcar_gen3: drivers: cpld
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:40:36 +02:00
Jorge Ramirez-Ortiz 070b0f0821 rcar_gen3: drivers: board identification
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:40:30 +02:00
Jorge Ramirez-Ortiz 0cdb86d41d rcar_gen3: drivers: avs [adaptive voltage scaling]
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:40:12 +02:00
Jorge Ramirez-Ortiz 2f473cc96a rcar_gen3: drivers: authentication
Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:39:49 +02:00
Jorge Ramirez-Ortiz 6ac2892a17 rcar_gen3: drivers: staging
- ddr
 - pfc [pin function controller]
 - qos [bandwidth]

checkpatch.pl is generating too many errors.
2018-10-17 18:39:43 +02:00
Jorge Ramirez-Ortiz 7e532c4bf7 rcar-gen3: initial commit for the rcar-gen3 boards
Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date:   Thu Aug 30 21:26:41 2018 +0900
	Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
  git@github.com:ARMmbed/mbedtls.git [devel]

  Merge: 68dbc94 f34a4c1
  Author: Simon Butcher <simon.butcher@arm.com>
  Date:   Thu Aug 30 00:57:28 2018 +0100

* optee_os:
  https://github.com/BayLibre/optee_os

  Until it gets merged into OP-TEE, the port requires Renesas' Trusted
  Environment with a modification to support power management.

  Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  Date:   Thu Aug 30 16:49:49 2018 +0200
    plat-rcar: cpu-suspend: handle the power level
    Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>

* u-boot:
  The port has beent tested using mainline uboot.

  Author: Fabio Estevam <festevam@gmail.com>
  Date:   Tue Sep 4 10:23:12 2018 -0300

*linux:
  The port has beent tested using mainline kernel.

  Author: Linus Torvalds <torvalds@linux-foundation.org>
  Date:   Sun Sep 16 11:52:37 2018 -0700
      Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to  BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----

* cpuidle
  -------
   enable kernel's cpuidle arm_idle driver and boot

* system suspend
  --------------
  $ cat suspend.sh
    #!/bin/bash
    i2cset -f -y 7 0x30 0x20 0x0F
    read -p "Switch off SW23 and press return " foo
    echo mem > /sys/power/state

* cpu hotplug:
  ------------
  $ cat offline.sh
    #!/bin/bash
    nbr=$1
    echo 0 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

  $ cat online.sh
    #!/bin/bash
    nbr=$1
    echo 1 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:38:33 +02:00
Andrew F. Davis 6a655a85c0 ti: k3: common: Do not disable cache on TI K3 core powerdown
Leave the caches on and explicitly flush any data that
may be stale when the core is powered down. This prevents
non-coherent interconnect access which has negative side-
effects on AM65x.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-10-16 09:27:53 -05:00
Roberto Vargas 32aee8415d scmi: Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled
When HW_ASSISTED_COHERENCY is enabled we can use spinlocks
instead of using the more complex and slower bakery algorithm.

Change-Id: I9d791a70050d599241169b9160a67e57d5506564
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-10-16 13:38:41 +01:00
Deepak Pandey da3b038fd5 plat/arm: relocate the jump_if_cpu_midr macro.
macro jump_if_cpu_midr is used commonly by many arm platform.
It has now been relocated to common place to remove duplication
of code.

Change-Id: Ic0876097dbc085df4f90eadb4b7687dde7c726da
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
2018-10-15 13:08:52 +05:30
Dimitris Papastamos 0a09313ec7
Merge pull request #1626 from Yann-lms/partition_verbose
drivers: partition: correct compilation error in VERBOSE mode
2018-10-12 17:45:56 +01:00
Dimitris Papastamos bd8c401614
Merge pull request #1627 from sandrine-bailleux-arm/sb/object-pool-allocator
Introduce object pool allocator
2018-10-12 17:45:31 +01:00
Dimitris Papastamos 776bd2b618
Merge pull request #1630 from antonio-nino-diaz-arm/an/fix-console
pl011: cnds: cbmem: 16550: Fix comments
2018-10-12 17:45:09 +01:00
Antonio Nino Diaz 65199dc844 pl011: cnds: cbmem: 16550: Fix comments
The comments with the prototypes of the register functions of the
console drivers are incorrect. The arguments are wrong. This patch fixes
them.

Change-Id: I38c4b481ee69e840780111c42f03c0752eb6315c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-12 14:47:41 +01:00
Soby Mathew 02126db803
Merge pull request #1615 from Andre-ARM/make_s
Makefile: Support totally quiet output with -s
2018-10-12 14:39:50 +01:00
Soby Mathew d9f529f598
Merge pull request #1606 from satheesbalya-arm/sb1_2603_misra_plat
plat/arm: Fix misra warnings in platform code
2018-10-12 14:19:28 +01:00
Soby Mathew a3f92142e2
Merge pull request #1622 from bryanodonoghue/master+imx7-mmc_fix
drivers: imx: mxc_usdhc: Do not set MMC_RSP_48 for MMC_RESPONSE_R2
2018-10-12 14:17:59 +01:00
Soby Mathew 3e75ea4d1a
Merge pull request #1624 from glneo/less-cache-flushing
PSCI cache flush and comment fixup
2018-10-12 14:16:57 +01:00
Sathees Balya 89509904c0 plat/arm: Fix misra warnings in platform code
Change-Id: Ica944acc474a099219d50b041cfaeabd4f3d362f
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
2018-10-11 17:01:07 +01:00
Sandrine Bailleux 9cc4651c9d Introduce object pool allocator
The object pool allocator provides a simplistic interface to manage
allocation in a fixed-size static array. The caller creates a static
"object pool" out of such an array and may then call pool_alloc() to
get the next available object within the pool. There is also a variant
to get multiple consecutive objects: pool_alloc_n().

Note that this interface does not provide any way to free the objects
afterwards. This is by design and it is not a limitation. We do not
want to introduce complexity induced by memory freeing, such as
use-after-free bugs, memory fragmentation and so on.

Change-Id: Iefc2e153767851fbde5841a295f92ae48adda71f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-10-11 16:11:18 +02:00
Yann Gautier e7f9ab4e5a drivers: partition: correct compilation error in VERBOSE mode
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2018-10-11 14:39:49 +02:00
Soby Mathew 424f68dd1d
Merge pull request #1625 from ldts/psci
psci: platform control of SYSTEM_SUSPEND entry
2018-10-11 13:37:53 +01:00
Antonio Nino Diaz 0f58d4f2c8 plat/arm: Remove file arm_board_def.h
This file is shared between FVP and all CSS platforms. While it may be
true that some definitions can be common, it doesn't make sense
conceptually. For example, the stack size depends on the platform and so
does the SRAM size.

After removing them, there are not enough common definitions to justify
having this header, so the other definitions have been moved to the
platform_def.h of FVP, board_css_def.h and arm_def.h.

Change-Id: Ifbf4b017227f9dfefa1a430f67d7d6baae6a4ba1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-11 13:02:34 +01:00
Soby Mathew e22a4ae074
Merge pull request #1621 from jts-arm/typos
Various corrections of typos
2018-10-11 12:00:48 +01:00
Soby Mathew 8b3345f4a6
Merge pull request #1619 from antonio-nino-diaz-arm/an/norflash
plat/arm: Move norflash driver to drivers/ folder
2018-10-11 11:59:37 +01:00
ldts a4065abdfb psci: platform control of SYSTEM_SUSPEND entry
Some platforms can only resume from system suspend from the boot
CPU, hence they should only enter that state from that same core.

The following commit presents an interface that allows the platform to
reject system suspend entry near its very last stage (last CPU).
2018-10-11 12:57:49 +02:00
Antonio Nino Diaz 58ea77a004 plat/arm: Move board_css_common.c to juno folder
This file is only used by Juno as all other CSS platforms have their own
private memory maps.

Change-Id: I1c9f27aac7b1d8bff4d92674e8bde5505b93c8c4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-11 09:58:34 +01:00
Soby Mathew 60a9dee5ca
Merge pull request #1620 from deepan02/deepak-arm/move-reset-to-bl31
plat/arm: allow RESET_TO_BL31 for CSS-based platforms
2018-10-11 09:55:00 +01:00
Andrew F. Davis f996a5f79f PSCI: Do not flush cache when unneeded
When a platform enables its caches before it accesses the
psci_non_cpu_pd_nodes structure then explicit cache maintenance
is not needed.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-10-10 13:07:56 -05:00
Andrew F. Davis c98db6c617 PSCI: Update comment on MMU disablement
The MMU is not disabled in this path, update the comment to
reflect this. Also clarify that both paths call prepare_cpu_pwr_dwn(),
but the second path does stack cache maintenance.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-10-10 13:07:56 -05:00
Soby Mathew f7a18268ad
Merge pull request #1614 from MISL-EBU-System-SW/integration-fix
Fix service CPU image load at BL2 stage and update maintainers list
2018-10-10 14:00:34 +01:00