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9 Commits

Author SHA1 Message Date
Yann Gautier afcdc9d8d7 fix(st-fmc): fix type in message 
As page is unsigned, we should use %u and not %d.
Find with -Wformat-signedness.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7205971ee5e83163e4fe47d33bb9e90832b59ae0
 2022-02-15 18:09:51 +01:00
Yann Gautier 33667d299b feat(st): use newly introduced clock framework 
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().

Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
 2021-12-22 13:08:09 +01:00
Yann Gautier 3ed016571a nand: stm32_fmc_nand: remove dead code 
The FMC driver in TF-A only supports NAND Mode 0 timings.
The timings are then hard-coded as macros, leading to some parts of code
unreachable.
This issue was found by Coverity scan: CID 366361.

Change-Id: I864c51ce11b9ef74ad82b3301f56f46a2e0f70ca
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
 2021-02-11 18:11:34 +01:00
Lionel Debieve 495885bce6 drivers: stm32_fmc2_nand: fix boundary check for chip select 
Chip select is retrieved from device tree and check
must be done regarding the MAX_CS defined.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Change-Id: I03144b133bd51a845a4794f0f6bbd9402fc04936
 2020-10-12 14:46:31 +02:00
Christophe Kerello 0c3e8acbd6 drivers: stm32_fmc2_nand: move to new bindings 
FMC node bindings are modified to add EBI controller node.
FMC driver and associated device tree files are modified
to support these new bindings.

Change-Id: I4bf201e96a1aca20957e0dac3a3b87caadd05bdc
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
 2020-10-12 14:46:07 +02:00
Lionel Debieve 44966000ec drivers: stm32_fmc2_nand: fix incorrect error detection 
Clear interrupt flag register after each sector read to avoid
issue when checking the register status.
Without clearing the interrupt, the status read doesn't wait
properly the ready bit.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: If290e3f165b986f0e736bb1b5e4d3dad4b749d74
 2020-10-08 09:42:04 +02:00
Etienne Carriere 45c70e6867 drivers: stm32_reset adapt interface to timeout argument 
Changes stm32mp1 reset driver to API to add a timeout argument
to stm32mp_reset_assert() and stm32mp_reset_deassert() and
a return value.

With a supplied timeout, the functions wait the target reset state
is reached before returning. With a timeout of zero, the functions
simply load target reset state in SoC interface and return without
waiting.

Helper functions stm32mp_reset_set() and stm32mp_reset_release()
use a zero timeout and return without a return code.

This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c
accordingly without any functional change.
functional change.

Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
 2020-06-01 08:38:20 +02:00
Yann Gautier 9fe181c6a6 nand: stm32_fmc2_nand: correct xor_ecc.val assigned value 
The variable is wrongly set to 0L, whereas it is an unsigned int, it should
then be 0U.

Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da238
Signed-off-by: Yann Gautier <yann.gautier@st.com>
 2020-03-23 16:42:33 +01:00
Lionel Debieve 695f7df852 fmc: stm32_fmc2_nand: Add FMC2 driver support 
Add fmc2_nand driver support. The driver implements
only read interface for NAND devices.

Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
 2020-01-20 11:32:59 +01:00