Some platforms might chose to take different actions depending on this
value; this is precisely the case for rcar-gen3.
Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
Add another level of abstraction of weak defs for
arm_bl2_handle_post_image_load to prevent two weak definitions
of the same function
Change-Id: Ie953786f43b0f88257c82956ffaa5fe0d19603db
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
A pointer to rt_svc_desc_t is defined both in the function
handle_runtime_svc() and globally. Since the value of the
pointer RT_SVC_DESCS_START is defined by the linker and
never changes make this definition local in both
handle_runtime_svc() and runtime_svc_init() to reduce the
number of loads
Change-Id: Iea42c778d8599a26c87700009163b5a8d7d60be2
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
This patch does two main things
- It implements the crash console UART init in assembly, as a
hard-coded 115200 8N1 assumed from the 24 MHz clock.
If the clock setup code has not run yet, this code can't work but,
setting up clocks and clock-gates is way out of scope for this type of
recovery function.
- It adds code to write a character out of the NXP UART without using any
stack-based operations when doing so.
- Provides support for crash console in DCE or DTE mode.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
- Adds a simple register read/write abstraction to cut-down on the
amount of typing and text required to access UART registers in this driver.
- Adds a console getc() callback.
- Adds a console putc() callback, translating '\n' to '\r' + '\n'.
- Initializes the MXC UART, take a crude method of calculating the
BAUD rate generator. The UART clock-gates must have been enabled prior
to launching the UART init code.
Special care needs to be taken to ensure the UBIR is initialized before the
UBMR and we need to ensure that UCR2.SRST comes good before trying to
program other registers associated with the UART.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
When any of these functions is called the backtrace will be printed to
the console.
Change-Id: Id60842df824b320c485a9323ed6b80600f4ebe35
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This function diplays the backtrace, the current EL and security state
to allow a post-processing tool to choose the right binary to interpret
the dump.
The output can be fed to GNU addr2line to resolve function names given
an ELF binary compiled with debug information. The "-i" flag is
recommended to improve display in case of inlined functions. The *.dump
files generated during the build process can also be used.
The function works in AArch64 and AArch32. In AArch32 it only works in
A32 mode (without T32 interworking), which is enforced in the Makefile.
Sample output of a backtrace at EL3:
BACKTRACE: START: function_name
0: EL3: 0x798
1: EL3: 0x538
2: EL3: 0x550
3: EL3: 0x55c
4: EL3: 0x568
5: EL3: 0x5a8
6: EL3: 0xf4
BACKTRACE: END: function_name
In order to enable it the new option ENABLE_BACKTRACE must be set to 1.
This option is set to 1 by default only in AArch64 debug builds. As
usual, it can be overridden by the platform makefile and in the build
command line.
Change-Id: Icaff39b0e5188329728be2f3c72b868b2368e794
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
At the moment the AArch32 instruction set isn't specified in the command
line, which means that the compiler is free to choose the one it sees
fit. This decision may change between compiler versions, so it is better
to specify it manually.
The build option AARCH32_INSTRUCTION_SET has been introduced for this
reason. This option can be set to T32 or A32 to pass the correct flags
to the compiler.
The current behaviour is to default to T32 due to it's smaller size.
Change-Id: I02297eb1d9404b5868ff7c054fbff9b3cda7fdb6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This patch fixes a bug in the context management code that causes it to
ignore the HANDLE_EA_EL3_FIRST compile-time option and instead always
configure SCR_EL3 to force all external aborts to trap into EL3. The
code used #ifdef to read compile-time option declared with add_define in
the Makefile... however, those options are always defined, they're just
defined to either 0 or 1, so #if is the correct syntax to check for
them. Also update the documentation to match.
This bug has existed since the Nov 2017 commit 76454abf4 (AArch64:
Introduce External Abort handling), which changed the
HANDLE_EA_EL3_FIRST option to use add_define.
Change-Id: I7189f41d0daee78fa2fcf4066323e663e1e04d3d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Folders drivers/st/ and include/drivers/st/ are added in maintainers.rst,
under STM32MP1 platform port.
This will allow notifications for the files modified there.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Currently in Linux maximum number of clocks is hard-coded and
so it needs to allocate static memory. It can get actual clock
number after querying all clock names by special clock name
string. Add new query data parameter to get actual number of
clocks so Linux can get actual clock numbers in advance.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Updated optee_utils.c to fixARM-software/tf-issues#603 related to the
tee-validate-header bug.
Minor updates to the header valid checking logic. It would never make
sense to have less than 1 image to load so this is now checked.
Changed OPTEE_MAX_IMAGE_NUM to OPTEE_MAX_NUM_IMAGES to clarify its
definition. OPTEE_MAX_IMAGE_NUM sounds like an ID assigned to the last
image to load. OPTEE_MAX_NUM_IMAGES sounds like the maximum number of
images to load.
Signed-off-by: Nathan Menhorn <nathan.menhorn@xilinx.com>
The initial implementation was corrupting registers that it shouldn't.
Now this is fixed.
Change-Id: Iaa407c18e668b2d9381391bf10d6876fe936aded
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Small patch which removes some redundant casts to (void *).
Change-Id: If1cfd68f2989bac1d39dbb3d1c31d4119badbc21
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
TI-SCI message protocol provides support for controlling of various
physical cores available in the SoC. In order to control which host is
capable of controlling a physical processor core, there is a processor
access control list that needs to be populated as part of the board
configuration data.
Introduce support for the set of TI-SCI message protocol APIs that
provide us with this capability of controlling physical cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Since system controller now has control over SoC power management, core
operation such as reset need to be explicitly requested to reboot the SoC.
Add support for this here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
TI-SCI message protocol provides support for management of various
hardware entities within the SoC.
In general, we expect to function at a device level of abstraction,
however, for proper operation of hardware blocks, many clocks directly
supplying the hardware block needs to be queried or configured.
Introduce support for the set of TI-SCI message protocol support that
provide us with this capability.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Andrew F. Davis
Jorge Ramirez-Ortiz
Dimitris Papastamos
Daniel Boulby
Bryan O'Donoghue
Antonio Nino Diaz
Jan Dabros
Douglas Raillard
Soby Mathew
Julius Werner
Nariman Poushin
Yann Gautier
Rajan Vaja
nathan-menhorn
John Tsichritzis