Stefan Chulski 6792ba1598 plat: marvell: ap806: implement workaround for errata-id FE-4265711 ... ERRATA ID: FE-4265711 - Incorrect CNTVAL reading CNTVAL reflects the global system counter value in binary format. Due to this erratum, the CNTVAL value presented to the processor may be incorrect for several clock cycles. Workaround: Override the default value of AP Register Device General control 20 [19:16] and AP Register Device General Control 21 [11:8] to the value of 0x3. Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>		2020-10-04 15:20:55 +02:00
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aarch64	plat: marvell: ap806: implement workaround for errata-id FE-4265711	2020-10-04 15:20:55 +02:00
ble	Use abspath to dereference $BUILD_BASE	2020-08-04 18:02:02 +01:00
include	plat: marvell: ap806: implement workaround for errata-id FE-4265711	2020-10-04 15:20:55 +02:00
mss	plat: marvell: t9130: pass actual CP count for load_image	2020-07-30 15:15:52 +02:00
a8k_common.mk	Merge changes I0826ef8b,I9b4659a1 into integration	2020-07-21 21:49:09 +00:00
plat_bl1_setup.c	marvell: armada: add extra level in marvell platform hierarchy	2020-06-07 00:06:03 +02:00
plat_bl31_setup.c	plat: marvell: a8k: move address config of cp1/2 to BL2	2020-06-19 17:58:54 +02:00
plat_ble_setup.c	plat: marvell: t9130: add SVC support	2020-07-30 15:15:52 +02:00
plat_pm.c	marvell: armada: add extra level in marvell platform hierarchy	2020-06-07 00:06:03 +02:00
plat_pm_trace.c	marvell: armada: add extra level in marvell platform hierarchy	2020-06-07 00:06:03 +02:00
plat_thermal.c	marvell: armada: add extra level in marvell platform hierarchy	2020-06-07 00:06:03 +02:00