arm-trusted-firmware/drivers/arm/gic
Ming Huang 5a5e0aac39 fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif
A RAS error may be triggered while offline core in OS. Error:
Uncorrected software error in the Distributor, with IERR=9,SERR=f.
Core put to sleep before its Group enables were cleared.

gicv3_cpuif_disable() will be called in offline core flow.
According to GIC architecture version 3 and version 4:
Architectural execution of a DSB instruction guarantees that
the last value written to ICC_IGRPEN0_EL1, ICC_IGRPEN1_EL1,
ICC_IGRPEN1_EL3 or GICC_CTLR.{EnableGrp0, EnableGrp1}is observed
by the associated Redistributor.
An ISB or other context synchronization operation must precede
the DSB to ensure visibility of System register writes.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: Iff1475657f401374c761b5e8f2f5b3a4b2040e9d
2021-07-23 10:48:00 +08:00
..
common TF-A GICv2 driver: Introduce makefile 2020-07-20 16:44:34 +00:00
v2 Fix casting bug in gicv2_main.c 2020-10-10 07:14:44 +00:00
v3 fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif 2021-07-23 10:48:00 +08:00