Andre Przywara c5346ed5e5 arm_fpga: Predefine DTB and BL33 load addresses ... The memory layout for the FPGA is fairly uniform for most of the FPGA images, and we already assume that DRAM starts at 2GB by default. Prepopulate PRELOADED_BL33_BASE and FPGA_PRELOADED_DTB_BASE to some sane default values, to simplify building some stock image. If people want to deviate from that, they can always override those addresses on the make command line. Change-Id: I2238fafb3f8253a01ad2d88d45827c141d9b29dd Signed-off-by: Andre Przywara <andre.przywara@arm.com>		2020-07-09 13:13:41 +01:00
..
aarch64	arm_fpga: Use Generic UART	2020-05-05 15:36:51 +01:00
include	arm_fpga: Read GICD and GICR base addresses from DT	2020-05-05 15:36:51 +01:00
fpga_bl31_setup.c	arm_fpga: Read generic timer counter frequency from DT	2020-05-05 15:36:51 +01:00
fpga_console.c	arm_fpga: Read UART address from DT	2020-05-05 15:36:51 +01:00
fpga_def.h	arm_fpga: Support more CPU clusters	2020-07-09 13:13:12 +01:00
fpga_gicv3.c	arm_fpga: Read GICD and GICR base addresses from DT	2020-05-05 15:36:51 +01:00
fpga_pm.c	Fix coverity defects found on the FPGA port.	2020-04-02 14:11:12 +01:00
fpga_private.h	plat/arm/board/arm_fpga: Initialize the Generic Interrupt Controller	2020-03-26 20:41:58 +00:00
fpga_topology.c	arm_fpga: Fix MPIDR topology checks	2020-06-26 13:08:55 +01:00
platform.mk	arm_fpga: Predefine DTB and BL33 load addresses	2020-07-09 13:13:41 +01:00