Hadi Asyrafi 13d33d52ce intel: Enable SiP SMC secure register access ... Enable access to secure registers by non-secure world through secure monitor calls Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I80610e08c7cf31f17f47a7597c269131a8de2491		2019-12-30 10:17:04 +08:00
..
aarch64	intel: stratix10: Enable uboot entrypoint support	2019-12-17 12:54:29 +08:00
drivers	intel: Refactor common platform code [5/5]	2019-11-28 12:47:58 +08:00
include	Merge changes from topic "mailbox-fixes" into integration	2019-12-19 17:33:03 +00:00
soc	intel: Introduce mailbox response length handling	2019-12-17 19:45:29 +08:00
bl2_plat_mem_params_desc.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00
socfpga_delay_timer.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00
socfpga_image_load.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00
socfpga_psci.c	intel: Modify BL31 address mapping	2019-12-17 12:54:34 +08:00
socfpga_sip_svc.c	intel: Enable SiP SMC secure register access	2019-12-30 10:17:04 +08:00
socfpga_storage.c	intel: Refactor common platform code [2/5]	2019-11-28 12:47:58 +08:00
socfpga_topology.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00