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Pritesh Raithatha 28f45bb83c Tegra186: smmu: add support for backup multiple smmu regs 
Modifying smmu macros to pass base address of smmu so that it can be
used with multiple smmus.

Added macro for combining smmu backup regs that can be used for multiple
smmus.

Change-Id: I4f3bb83d66d5df14a3b91bc82f7fc26ec8e4592e
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
 		2019-01-31 08:45:22 -08:00
..
allwinner Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
arm fvp: pwrc: Move to drivers/ folder 2019-01-25 16:04:11 +00:00
common Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
hisilicon Move BL1 and BL2 private defines to bl_common.h 2019-01-15 13:52:32 +00:00
imx imx: power optimization for i.mx8qx 2019-01-29 09:26:41 +08:00
layerscape Move BL1 and BL2 private defines to bl_common.h 2019-01-15 13:52:32 +00:00
marvell Merge pull request #1745 from svenauhagen/bugfix/a8k 2019-01-31 10:22:50 +00:00
mediatek plat/arm: Sanitise includes 2019-01-25 16:04:10 +00:00
meson/gxbb Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
nvidia/tegra Tegra186: smmu: add support for backup multiple smmu regs 2019-01-31 08:45:22 -08:00
qemu Move BL1 and BL2 private defines to bl_common.h 2019-01-15 13:52:32 +00:00
renesas/rcar rcar_gen3: plat: Add missing cpu_on_check() implementation 2019-01-29 06:07:21 +01:00
rockchip rockchip: Fix GICv2 interrupts 2019-01-28 14:35:50 +00:00
rpi3 Merge pull request #1788 from laroche/rpi3_duplicate_initialization 2019-01-29 13:44:10 +00:00
socionext SPM: Rename SPM_DEPRECATED flag to SPM_MM 2019-01-22 09:20:59 +00:00
st/stm32mp1 stm32mp1: set ETZPC controlled peripherals and GPIOZ as non-secure 2019-01-18 15:45:08 +01:00
ti/k3 ti: k3: common: Add support for runtime detection of GICR base address 2019-01-22 13:11:09 -06:00
xilinx plat/arm: Sanitise includes 2019-01-25 16:04:10 +00:00