0943ea379f
MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a |
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.. | ||
aarch64 | ||
include | ||
soc | ||
bl2_plat_mem_params_desc.c | ||
bl2_plat_setup.c | ||
bl31_plat_setup.c | ||
plat_delay_timer.c | ||
plat_psci.c | ||
plat_sip_svc.c | ||
plat_storage.c | ||
plat_topology.c | ||
platform.mk | ||
platform_def.h | ||
stratix10_image_load.c |