Tien Hock, Loh 0943ea379f plat/intel: Fix SMPLSEL for MMC ... MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a		2019-07-10 11:39:03 +08:00
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plat_macros.S	plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform	2019-02-26 09:25:14 +08:00
platform_private.h	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
s10_clock_manager.h	intel: Enable watchdog timer on Intel S10 platform	2019-03-21 10:35:24 +08:00
s10_handoff.h	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
s10_mailbox.h	plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform	2019-02-26 09:25:14 +08:00
s10_memory_controller.h	plat: intel: Fix faulty DDR calibration value	2019-02-13 14:39:31 +08:00
s10_noc.h	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
s10_pinmux.h	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
s10_reset_manager.h	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
s10_system_manager.h	plat/intel: Fix SMPLSEL for MMC	2019-07-10 11:39:03 +08:00