ae7a93521f
Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE and TZRAM_SIZE for DDR secure regions), we can split them and don't have to hardcode the range in two places. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> |
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addressmap_shared.h | ||
bl31_param.h | ||
dram_regs.h | ||
m0_param.h | ||
misc_regs.h | ||
pmu_bits.h | ||
pmu_regs.h |