Manish V Badarkhe 40ff907470 feat(trbe): initialize trap settings of trace buffer control registers access ... Trap bits of trace buffer control registers access are in architecturally UNKNOWN state at boot hence 1. Initialized these bits to zero to prohibit trace buffer control registers accesses in lower ELs (EL2, EL1) in all security states when FEAT_TRBE is implemented 2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and hence setting it to zero also aligns with the Arm ARM reference recommendation, that mentions software must writes RES0 bits with all 0s Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>		2021-08-25 18:01:16 +01:00
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aarch32	Add PIE support for AARCH32	2021-04-21 15:05:57 +02:00
aarch64	feat(trbe): initialize trap settings of trace buffer control registers access	2021-08-25 18:01:16 +01:00