Abhyuday Godhasara 4156719550 fix(plat/xilinx/versal): resolve misra R15.6 in pm services ... MISRA Violation: MISRA-C:2012 R.15.6 - The body of an iteration-statement or a selection-statement shall be a compound statement Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> Change-Id: I82e924a77ee3afeb56fa18714e94cc4f6fff5a49		2021-11-30 01:54:51 -08:00
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aarch64	xilinx: versal: PLM to ATF handover	2020-01-23 03:01:22 -07:00
include	fix(plat/xilinx/versal/include): correct IPI buffer offset	2021-05-25 07:02:49 -07:00
pm_service	fix(plat/xilinx/versal): resolve misra R15.6 in pm services	2021-11-30 01:54:51 -08:00
bl31_versal_setup.c	plat: xilinx: Error management support	2021-04-22 22:47:12 +02:00
plat_psci.c	plat: xilinx: versal: Mark IPI calls secure/non-secure	2021-03-19 07:47:12 -07:00
plat_topology.c	arm64: versal: Add support for new Xilinx Versal ACAPs	2018-11-09 15:06:53 +05:30
plat_versal.c	plat: xilinx: Fix non-MISRA compliant code	2021-01-10 20:48:09 -07:00
platform.mk	feat(plat/versal): add support for SLS mitigation	2021-07-20 22:33:47 -06:00
sip_svc_setup.c	xilinx: versal: enable ipi mailbox service	2020-01-15 11:02:37 -08:00
versal_gicv3.c	plat: xilinx: versal: Move versal_private.h to include directory	2020-01-15 11:01:28 -08:00
versal_ipi.c	xilinx: Add support to send PM API to PMC using IPI for versal	2020-01-15 11:01:37 -08:00