Caesar Wang 4d5d98c77c rockchip: fixes the clock select and divide register for rk3399 ... As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON register. As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the CRU_CLKSEL_CON offset is 0x100,not 0x80. Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529		2016-09-29 00:51:19 +08:00
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arm	Merge pull request #717 from sandrine-bailleux-arm/sb/foundation-fvp-v10	2016-09-26 10:20:08 +01:00
common	AArch32: Common changes needed for BL1/BL2	2016-09-21 16:27:15 +01:00
compat	AArch32: Add essential ARM platform and FVP support	2016-08-10 18:01:38 +01:00
mediatek	Remove MT6795 plat_sip_svc.c to fix Coverity analysis error.	2016-09-19 14:20:42 +08:00
nvidia/tegra	Migrate platform makefile to new console driver location	2016-08-09 17:33:57 +01:00
qemu	Migrate platform makefile to new console driver location	2016-08-09 17:33:57 +01:00
rockchip	rockchip: fixes the clock select and divide register for rk3399	2016-09-29 00:51:19 +08:00
xilinx/zynqmp	zynqmp: Make MMIO write FW call synchronous	2016-09-13 09:19:03 -07:00