Louis Mayencourt f1be00da0b Use correct type when reading SCR register ... The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2020-01-28 11:10:48 +00:00
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aarch32	rockchip: add common aarch32 support	2019-04-25 13:37:56 +02:00
aarch64	rockchip: move pmusram assembler code to a aarch64 subdir	2019-04-25 13:37:56 +02:00
drivers	rockchip: Allow socs with undefined wfe check bits	2019-04-25 13:37:56 +02:00
include	Merge changes from topic "rockchip-uart-fixes" into integration	2019-08-15 15:30:13 +00:00
pmusram	Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__	2019-08-01 13:14:12 -07:00
bl31_plat_setup.c	rockchip: move dt-coreboot uart distinction into param handling code	2019-08-09 09:40:19 +02:00
params_setup.c	plat/rockchip: initialize reset and poweroff GPIOs with known invalid value	2019-11-17 12:38:24 -08:00
plat_pm.c	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
plat_topology.c	rockchip: add common aarch32 support	2019-04-25 13:37:56 +02:00
rockchip_gicv2.c	rockchip: Fix GICv2 interrupts	2019-01-28 14:35:50 +00:00
rockchip_gicv3.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
rockchip_sip_svc.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
sp_min_plat_setup.c	rockchip: move dt-coreboot uart distinction into param handling code	2019-08-09 09:40:19 +02:00