Yatharth Kochar 6083c841d0 GICv3: Allow either G1S or G0 interrupts to be configured ... Currently the GICv3 driver mandates that platform populate both G1S and G0 interrupts. However, it is possible that a given platform is not interested in both the groups and just needs to specify either one of them. This patch modifies the `gicv3_rdistif_init()` & `gicv3_distif_init()` functions to allow either G1S or G0 interrupts to be configured. Fixes ARM-software/tf-issues#400 Change-Id: I43572b0e08ae30bed5af9334f25d35bf439b0d2b		2016-09-12 16:19:08 +01:00
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gicv3_helpers.c	Rework type usage in Trusted Firmware	2016-07-18 17:52:15 +01:00
gicv3_main.c	GICv3: Allow either G1S or G0 interrupts to be configured	2016-09-12 16:19:08 +01:00
gicv3_private.h	AArch32: Enable GIC and TZC support	2016-08-10 12:35:46 +01:00