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Eleanor Bonnici 6de9b3364b Cortex-A72: Implement workaround for erratum 859971 
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.

Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
 		2017-09-07 14:22:02 +01:00
..
aem_generic.S Use SPDX license identifiers 2017-05-03 09:39:28 +01:00
cortex_a32.S Use SPDX license identifiers 2017-05-03 09:39:28 +01:00
cortex_a53.S CPU: Correct names of implementation-defined aux regs 2017-08-29 13:52:48 +01:00
cortex_a57.S Cortex-A57: Implement workaround for erratum 859972 2017-09-07 14:22:02 +01:00
cortex_a72.S Cortex-A72: Implement workaround for erratum 859971 2017-09-07 14:22:02 +01:00
cpu_helpers.S aarch32: Implement cpu_rev_var_hs() 2017-06-20 15:14:01 +01:00