arm-trusted-firmware/drivers/marvell
Pali Rohár b9185c75f7 fix(plat/marvell/a3720/uart): fix configuring UART clock
When configuring the UART_BAUD_REG register, the function
console_a3700_core_init() currently only changes the baud divisor field,
leaving other fields to their previous value.

This is incorrect, because the baud divisor is computed with the
assumption that the parent clock rate is 25 MHz, and since the other
fields in this register configure the parent clock, which could have
been changed by U-Boot or Linux.

Fix this function to also configure the other fields so that the UART
parent clock is selected to be the xtal clock.

For example without this change TF-A prints only

    ERROR: a3700_system_off needs to be implemented

followed by garbage after plat_crash_console_init() is called.

After applying this change instead of garbage it also print crash info:

    PANIC at PC : 0x0000000004023800

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I72f338355cc60d939b8bb978d9c7fdd576416b81
2021-06-01 16:32:10 +02:00
..
comphy drivers: marvell: comphy: add rx training on 10G port 2021-04-20 13:00:03 +02:00
mc_trustzone Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
mg_conf_cm3 drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW 2020-07-10 10:55:09 +00:00
mochi drivers/marvell: check if TRNG unit is present 2021-04-20 13:00:16 +02:00
secure_dfx_access drivers: marvell: misc-dfx: extend dfx whitelist 2021-04-20 12:59:45 +02:00
uart fix(plat/marvell/a3720/uart): fix configuring UART clock 2021-06-01 16:32:10 +02:00
amb_adec.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
ap807_clocks_init.c ble: ap807: improve PLL configuration sequence 2020-06-07 00:06:03 +02:00
cache_llc.c drivers: marvell: Fix the LLC SRAM driver 2020-07-10 10:55:33 +00:00
ccu.c plat: marvell: armada: add ccu window for workaround errata-id 3033912 2020-10-04 15:23:29 +02:00
comphy.h Standardise header guards across codebase 2018-11-08 10:20:19 +00:00
ddr_phy_access.c ddr_phy: use smc calls to access ddr phy registers 2021-04-20 12:59:34 +02:00
ddr_phy_access.h ddr_phy: use smc calls to access ddr phy registers 2021-04-20 12:59:34 +02:00
gwin.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
io_win.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
iob.c marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1 2021-02-11 09:43:18 +00:00
mci.c plat: marvell: mci: perform mci link tuning for all mci interfaces 2020-06-07 00:06:03 +02:00
thermal.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00