7808b06b99
The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an offload engine for BPMP to do voltage related sequencing and for hardware requests to be handled in a better latency than BPMP-firmware. There are two interfaces to the MCEs - Abstract Request Interface (ARI) and the traditional NVGINDEX/NVGDATA interface. MCE supports various commands which can be used by CPUs - ARM as well as Denver, for power management and reset functionality. Since the linux kernel is the master for all these scenarios, each MCE command can be issued by a corresponding SMC. These SMCs have been moved to SiP SMC space as they are specific to the Tegra186 SoC. Change-Id: I67bee83d2289a8ab63bc5556e5744e5043803e51 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> |
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| arm | ||
| common | ||
| compat | ||
| mediatek | ||
| nvidia/tegra | ||
| qemu | ||
| rockchip | ||
| xilinx/zynqmp | ||