Varun Wadekar aa1bdc960c Tegra186: fix per-cpu wake times for CPU power states ... This patch fixes the logic used to calculate the CPU index for storing the per-cpu wake times. We use the MIDR register to calculate the CPU index now. This allows us to store values for Denver/A57 CPUs properly. Change-Id: I9df0377afd4b92bbdaea495c0df06a9780a99d09 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2017-03-20 09:14:16 -07:00
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drivers	Tegra186: support for C6/C7 CPU_SUSPEND states	2017-03-20 09:13:52 -07:00
plat_psci_handlers.c	Tegra186: fix per-cpu wake times for CPU power states	2017-03-20 09:14:16 -07:00
plat_secondary.c	Tegra186: power on/off secondary CPUs	2017-03-20 09:12:02 -07:00
plat_setup.c	Tegra186: support for the latest platform port handlers	2017-03-20 09:13:25 -07:00
plat_sip_calls.c	Tegra186: add Video memory carveout settings	2017-03-20 09:14:05 -07:00
platform_t186.mk	Tegra186: relocate bl31.bin to the SYSRAM	2017-03-20 09:12:33 -07:00