e10842167b
The BL2 fills in the UART controller ID to be used as the normal as well as the crash console on Tegra platforms. The controller ID to UART controller base address mapping is handled by each Tegra SoC the base addresses might change across Tegra chips. This patch adds the handler to parse the platform params to get the UART ID for the per-soc handlers. Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> |
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| .. | ||
| arm | ||
| common | ||
| compat | ||
| mediatek | ||
| nvidia/tegra | ||
| qemu | ||
| rockchip | ||
| xilinx/zynqmp | ||