arm-trusted-firmware/plat
Chandni Cherukuri 8e1cc44900 sgi: disable CPU power down bit in reset handler
On SGI platforms, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1'
register requires an explicit write to clear it for hotplug and
idle to function correctly. The reset value of this bit is zero
but it still requires this explicit clear to zero. This indicates
that this could be a model related issue but for now this issue can
be fixed be clearing the CORE_PWRDN_EN in the platform specific
reset handler function.

Change-Id: I4222930daa9a3abacdace6b7c3f4a5472ac0cb19
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2018-08-03 16:17:33 +05:30
..
allwinner PSCI: Fix types of definitions 2018-07-20 13:49:22 +01:00
arm sgi: disable CPU power down bit in reset handler 2018-08-03 16:17:33 +05:30
common Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra 2018-07-25 16:09:54 +01:00
compat Do not enable SVE on pre-v8.2 platforms 2017-11-30 17:45:23 +00:00
hisilicon Merge pull request #1494 from hzhuang1/pcie_pin 2018-07-27 11:02:36 +01:00
imx PSCI: Fix types of definitions 2018-07-20 13:49:22 +01:00
layerscape PSCI: Fix types of definitions 2018-07-20 13:49:22 +01:00
marvell plat: marvell: Add board support for A8K platform 2018-07-18 18:48:30 +03:00
mediatek PSCI: Fix types of definitions 2018-07-20 13:49:22 +01:00
nvidia/tegra Tegra: Fix up INFO() message 2018-07-13 11:31:17 +02:00
qemu PSCI: Fix types of definitions 2018-07-20 13:49:22 +01:00
rockchip PSCI: Fix types of definitions 2018-07-20 13:49:22 +01:00
rpi3 xlat: Fix MISRA defects 2018-07-30 09:30:15 +01:00
socionext Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra 2018-07-25 16:09:54 +01:00
st/stm32mp1 stm32mp1: Link BL2, BL32 and DTB in one binary 2018-07-24 17:18:41 +02:00
ti/k3 ti: k3: common: Only enable caches early 2018-07-26 14:31:06 -05:00
xilinx/zynqmp Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra 2018-07-25 16:09:54 +01:00