Chandni Cherukuri 8e1cc44900 sgi: disable CPU power down bit in reset handler ... On SGI platforms, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an explicit write to clear it for hotplug and idle to function correctly. The reset value of this bit is zero but it still requires this explicit clear to zero. This indicates that this could be a model related issue but for now this issue can be fixed be clearing the CORE_PWRDN_EN in the platform specific reset handler function. Change-Id: I4222930daa9a3abacdace6b7c3f4a5472ac0cb19 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>		2018-08-03 16:17:33 +05:30
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common	Add support for SCMI AP core configuration protocol v1.0	2018-07-12 10:09:12 +01:00
drivers	CSS: Use SCMI AP core protocol to set the warm boot entrypoint	2018-07-12 10:09:12 +01:00
sgi	sgi: disable CPU power down bit in reset handler	2018-08-03 16:17:33 +05:30