Chandni Cherukuri 8e1cc44900 sgi: disable CPU power down bit in reset handler ... On SGI platforms, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an explicit write to clear it for hotplug and idle to function correctly. The reset value of this bit is zero but it still requires this explicit clear to zero. This indicates that this could be a model related issue but for now this issue can be fixed be clearing the CORE_PWRDN_EN in the platform specific reset handler function. Change-Id: I4222930daa9a3abacdace6b7c3f4a5472ac0cb19 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>		2018-08-03 16:17:33 +05:30
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aarch64	sgi: disable CPU power down bit in reset handler	2018-08-03 16:17:33 +05:30
fdts	sgi/dyncfg: add dts files to enable support for dynamic config	2018-06-15 10:17:11 +05:30
include	RAS: SGI575: Add platform specific RAS changes	2018-07-26 22:10:27 +05:30
sgi-common.mk	RAS: SGI: Add flags needed to build components for RAS feature	2018-07-26 22:13:44 +05:30
sgi_bl1_setup.c	ARM platforms: Add support for SGI575	2018-03-28 14:53:26 +01:00
sgi_bl31_setup.c	RAS: SGI: Add platform handler for RAS interrupts	2018-07-26 22:03:32 +05:30
sgi_image_load.c	sgi/dyncfg: add system-id node in hw-config dtb	2018-06-15 10:17:24 +05:30
sgi_interconnect.c	ARM platforms: Add support for SGI575	2018-03-28 14:53:26 +01:00
sgi_plat.c	RAS: SGI575: Add platform specific RAS changes	2018-07-26 22:10:27 +05:30
sgi_plat_config.c	css/sgi: remove redundant copy of gic driver data	2018-05-16 12:11:34 +05:30
sgi_ras.c	RAS: SGI575: Add platform specific RAS changes	2018-07-26 22:10:27 +05:30
sgi_security.c	ARM platforms: Add support for SGI575	2018-03-28 14:53:26 +01:00
sgi_topology.c	css/sgi: rework the core position calculation function	2018-05-16 12:11:41 +05:30