Marek Vasut 993d809cc1 feat(drivers/rcar3): add extra offset if booting B-side ... In case MFISBTSTSR bit 4 is 1, that means the loader was started as B-side. Load the remaining boot components from 8 MiB offset. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I11d882f30ca4f0cf55fd28d3470ff1063d350d10		2021-09-12 01:13:48 +02:00
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auth	drivers: renesas: auth: Move to common	2021-01-13 13:03:49 +00:00
avs	drivers: renesas: avs: Move to common	2021-01-13 13:03:49 +00:00
console	fix(drivers/rcar3): console: fix a return value of console_rcar_init	2021-09-12 01:13:48 +02:00
ddr	feat(plat/rcar3): update DDR setting for R-Car D3	2021-09-12 01:13:48 +02:00
delay	drivers: renesas: delay: Move to common	2021-01-13 13:03:48 +00:00
dma	drivers: renesas: dma: Move to common	2021-01-13 13:03:49 +00:00
emmc	fix(drivers/rcar3): fix CPG registers redefinition	2021-07-10 17:35:20 +02:00
iic_dvfs	fix(drivers/rcar3): i2c_dvfs: fix I2C operation	2021-07-10 17:35:23 +02:00
io	feat(drivers/rcar3): add extra offset if booting B-side	2021-09-12 01:13:48 +02:00
pwrc	feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR	2021-09-12 01:13:48 +02:00
rom	drivers: renesas: rom: Move to common	2021-01-13 13:03:48 +00:00
rpc	drivers: renesas: rpc: Move to common	2021-01-13 13:03:49 +00:00
scif	feat(plat/rcar3): add process of SSCG setting for R-Car D3	2021-09-12 01:13:48 +02:00
watchdog	feat(plat/rcar3): modify SWDT counter setting for R-Car D3	2021-09-12 01:13:48 +02:00
common.c	fix(drivers/rcar3): fix CPG registers redefinition	2021-07-10 17:35:20 +02:00
ddr_regs.h	drivers: renesas: Move ddr/qos/qos header files	2021-01-13 13:03:49 +00:00
pfc_regs.h	drivers: renesas: Move ddr/qos/qos header files	2021-01-13 13:03:49 +00:00
qos_reg.h	drivers: renesas: Move ddr/qos/qos header files	2021-01-13 13:03:49 +00:00