Toshiyuki Ogasahara 5460f82806 feat(plat/rcar3): modify LifeC register setting for R-Car D3 ... Modified SECGRP0COND6 and SECGRP1COND6 setting for R-Car D3. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I3f173ac44c11743965c013ef238748b0dc8cabab		2021-09-12 01:13:48 +02:00
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aarch64	feat(plat/rcar3): add process to back up X6 and X7 register's value	2021-09-12 01:13:48 +02:00
include	feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up	2021-09-12 01:13:48 +02:00
bl2_cpg_init.c	feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3	2021-09-12 01:13:48 +02:00
bl2_interrupt_error.c	plat: renesas: Move to common	2021-01-13 13:03:49 +00:00
bl2_plat_mem_params_desc.c	plat: renesas: Move to common	2021-01-13 13:03:49 +00:00
bl2_secure_setting.c	feat(plat/rcar3): modify LifeC register setting for R-Car D3	2021-09-12 01:13:48 +02:00
bl31_plat_setup.c	plat: renesas: Move to common	2021-01-13 13:03:49 +00:00
common.mk	feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537	2021-09-12 01:13:48 +02:00
plat_image_load.c	plat: renesas: Move to common	2021-01-13 13:03:49 +00:00
plat_pm.c	plat: renesas: common: Include ulcb_cpld.h conditionally	2021-01-13 13:03:49 +00:00
plat_storage.c	plat: renesas: Move to common	2021-01-13 13:03:49 +00:00
plat_topology.c	plat: renesas: Move to common	2021-01-13 13:03:49 +00:00
rcar_common.c	refactor(plat/ea_handler): Use default ea handler implementation for panic	2021-08-13 11:12:11 +02:00