220 lines
6.7 KiB
C
220 lines
6.7 KiB
C
/*
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* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include "msm8916_gicv2.h"
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#include <msm8916_mmap.h>
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#include <platform_def.h>
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#include <uartdm_console.h>
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static const mmap_region_t msm8916_mmap[] = {
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MAP_REGION_FLAT(PCNOC_BASE, PCNOC_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
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MAP_REGION_FLAT(APCS_BASE, APCS_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
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{},
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};
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static struct {
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entry_point_info_t bl32;
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entry_point_info_t bl33;
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} image_ep_info = {
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/* BL32 entry point */
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SET_STATIC_PARAM_HEAD(bl32, PARAM_EP, VERSION_1,
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entry_point_info_t, SECURE),
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.bl32.pc = BL32_BASE,
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/* BL33 entry point */
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SET_STATIC_PARAM_HEAD(bl33, PARAM_EP, VERSION_1,
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entry_point_info_t, NON_SECURE),
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.bl33.pc = PRELOADED_BL33_BASE,
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.bl33.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
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};
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static console_t console;
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unsigned int plat_get_syscnt_freq2(void)
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{
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return PLAT_SYSCNT_FREQ;
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}
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#define CLK_ENABLE BIT_32(0)
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#define CLK_OFF BIT_32(31)
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#define GPIO_BLSP_UART2_TX 4
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#define GPIO_BLSP_UART2_RX 5
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#define GPIO_CFG_FUNC_BLSP_UART2 (U(0x2) << 2)
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#define GPIO_CFG_DRV_STRENGTH_16MA (U(0x7) << 6)
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#define GCC_BLSP1_AHB_CBCR (GCC_BASE + 0x01008)
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#define GCC_BLSP1_UART2_APPS_CBCR (GCC_BASE + 0x0302c)
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#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x45004)
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#define BLSP1_AHB_CLK_ENA BIT_32(10)
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/*
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* The previous boot stage seems to disable most of the UART setup before exit
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* so it must be enabled here again before the UART console can be used.
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*/
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static void msm8916_enable_blsp_uart2(void)
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{
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/* Route GPIOs to BLSP UART2 */
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mmio_write_32(TLMM_GPIO_CFG(GPIO_BLSP_UART2_TX),
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GPIO_CFG_FUNC_BLSP_UART2 | GPIO_CFG_DRV_STRENGTH_16MA);
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mmio_write_32(TLMM_GPIO_CFG(GPIO_BLSP_UART2_RX),
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GPIO_CFG_FUNC_BLSP_UART2 | GPIO_CFG_DRV_STRENGTH_16MA);
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/* Enable AHB clock */
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mmio_setbits_32(GCC_APCS_CLOCK_BRANCH_ENA_VOTE, BLSP1_AHB_CLK_ENA);
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while (mmio_read_32(GCC_BLSP1_AHB_CBCR) & CLK_OFF)
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;
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/* Enable BLSP UART2 clock */
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mmio_setbits_32(GCC_BLSP1_UART2_APPS_CBCR, CLK_ENABLE);
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while (mmio_read_32(GCC_BLSP1_UART2_APPS_CBCR) & CLK_OFF)
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;
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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/* Initialize the debug console as early as possible */
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msm8916_enable_blsp_uart2();
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console_uartdm_register(&console, BLSP_UART2_BASE);
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}
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void bl31_plat_arch_setup(void)
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{
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mmap_add_region(BL31_BASE, BL31_BASE, BL31_END - BL31_BASE,
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MT_RW_DATA | MT_SECURE);
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
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BL_RO_DATA_END - BL_RO_DATA_BASE,
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MT_RO_DATA | MT_SECURE);
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mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
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mmap_add(msm8916_mmap);
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init_xlat_tables();
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enable_mmu_el3(0);
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}
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static void msm8916_configure_timer(void)
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{
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/* Set timer frequency */
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mmio_write_32(APCS_QTMR + CNTCTLBASE_CNTFRQ, plat_get_syscnt_freq2());
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/* Make frame 0 available to non-secure world */
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mmio_write_32(APCS_QTMR + CNTNSAR, BIT_32(CNTNSAR_NS_SHIFT(0)));
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mmio_write_32(APCS_QTMR + CNTACR_BASE(0),
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BIT_32(CNTACR_RPCT_SHIFT) | BIT_32(CNTACR_RVCT_SHIFT) |
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BIT_32(CNTACR_RFRQ_SHIFT) | BIT_32(CNTACR_RVOFF_SHIFT) |
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BIT_32(CNTACR_RWVT_SHIFT) | BIT_32(CNTACR_RWPT_SHIFT));
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}
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/*
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* The APCS register regions always start with a SECURE register that should
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* be cleared to 0 to only allow secure access. Since BL31 handles most of
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* the CPU power management, most of them can be cleared to secure access only.
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*/
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#define APCS_GLB_SECURE_STS_NS BIT_32(0)
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#define APCS_GLB_SECURE_PWR_NS BIT_32(1)
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#define APCS_BOOT_START_ADDR_SEC (APCS_CFG + 0x04)
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#define REMAP_EN BIT_32(0)
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#define APCS_AA64NAA32_REG (APCS_CFG + 0x0c)
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static void msm8916_configure_cpu_pm(void)
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{
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unsigned int cpu;
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/* Disallow non-secure access to boot remapper / TCM registers */
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mmio_write_32(APCS_CFG, 0);
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/*
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* Disallow non-secure access to power management registers.
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* However, allow STS and PWR since those also seem to control access
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* to CPU frequency related registers (e.g. APCS_CMD_RCGR). If these
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* bits are not set, CPU frequency control fails in the non-secure world.
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*/
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mmio_write_32(APCS_GLB, APCS_GLB_SECURE_STS_NS | APCS_GLB_SECURE_PWR_NS);
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/* Disallow non-secure access to L2 SAW2 */
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mmio_write_32(APCS_L2_SAW2, 0);
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/* Disallow non-secure access to CPU ACS and SAW2 */
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for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) {
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mmio_write_32(APCS_ALIAS_ACS(cpu), 0);
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mmio_write_32(APCS_ALIAS_SAW2(cpu), 0);
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}
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/* Make sure all further warm boots end up in BL31 and aarch64 state */
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CASSERT((BL31_BASE & 0xffff) == 0, assert_bl31_base_64k_aligned);
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mmio_write_32(APCS_BOOT_START_ADDR_SEC, BL31_BASE | REMAP_EN);
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mmio_write_32(APCS_AA64NAA32_REG, 1);
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}
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/*
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* MSM8916 has a special "interrupt aggregation logic" in the APPS SMMU,
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* which allows routing context bank interrupts to one of 3 interrupt numbers
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* ("TZ/HYP/NS"). Route all interrupts to the non-secure interrupt number
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* by default to avoid special setup on the non-secure side.
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*/
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#define GCC_SMMU_CFG_CBCR (GCC_BASE + 0x12038)
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#define GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x4500c)
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#define SMMU_CFG_CLK_ENA BIT_32(12)
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#define APPS_SMMU_INTR_SEL_NS (APPS_SMMU_QCOM + 0x2000)
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#define APPS_SMMU_INTR_SEL_NS_EN_ALL U(0xffffffff)
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static void msm8916_configure_smmu(void)
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{
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/* Enable SMMU configuration clock to enable register access */
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mmio_setbits_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA);
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while (mmio_read_32(GCC_SMMU_CFG_CBCR) & CLK_OFF)
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;
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/* Route all context bank interrupts to non-secure interrupt */
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mmio_write_32(APPS_SMMU_INTR_SEL_NS, APPS_SMMU_INTR_SEL_NS_EN_ALL);
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/* Disable configuration clock again */
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mmio_clrbits_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA);
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}
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void bl31_platform_setup(void)
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{
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INFO("BL31: Platform setup start\n");
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generic_delay_timer_init();
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msm8916_configure_timer();
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msm8916_gicv2_init();
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msm8916_configure_cpu_pm();
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msm8916_configure_smmu();
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INFO("BL31: Platform setup done\n");
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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switch (type) {
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case SECURE:
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return &image_ep_info.bl32;
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case NON_SECURE:
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return &image_ep_info.bl33;
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default:
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assert(sec_state_is_valid(type));
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return NULL;
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}
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}
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