Derek Basehore c6e15d1437 rockchip: rk3399: fix hang in ddr set rate ... This fixes a hang with setting the DRAM rate based on a race condition with the M0 which sets the DRAM rate. The AP can also starve the M0, so this also delays the AP reads to the DONE parameter for the M0. Signed-off-by: Derek Basehore <dbasehore@chromium.org>		2017-02-24 20:07:44 +08:00
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m0_ctl.c	rockchip: rk3399: fix hang in ddr set rate	2017-02-24 20:07:44 +08:00
m0_ctl.h	rk3399: dram: use PMU M0 to do ddr frequency scaling	2017-02-24 20:07:44 +08:00
plat_pmu_macros.S	Fix incorrect copyright notices	2016-12-14 14:31:32 +00:00
pmu.c	rockchip: rk3399: add support for ddrfreq suspend/resume	2017-02-24 20:07:44 +08:00
pmu.h	rockchip: close the PD center logic during suspend	2016-10-27 07:14:42 +08:00
pmu_fw.c	rockchip: add M0 source code and build system for RK3399	2016-10-25 03:29:42 +08:00
pmu_regs.h	rockchip: move pmu registers into another header for rk3399	2016-10-27 01:50:03 +08:00