Soby Mathew a91e12fbea Fix race in GIC IPRIORITY and ITARGET accessors ... GICD_IPRIORITYR and GICD_ITARGETSR specifically support byte addressing so that individual interrupt priorities can be atomically updated by issuing a single byte write. The previous implementation of gicd_set_ipriority() and gicd_set_itargetsr() used 32-bit register accesses, modifying values for 4 interrupts at a time, using a read-modify-write approach. This potentially may cause concurrent changes by other CPUs to the adjacent interrupts to be corrupted. This patch fixes the issue by modifying these accessors to use byte addressing. Fixes ARM-software/tf-issues#343 Change-Id: Iec28b5f5074045b00dfb8d5f5339b685f9425915		2016-02-09 16:50:36 +00:00
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arm	Fix race in GIC IPRIORITY and ITARGET accessors	2016-02-09 16:50:36 +00:00
auth	Always build with '-pedantic'	2016-01-05 11:41:08 +00:00
console	Disable PL011 UART before configuring it	2016-01-21 17:27:47 +00:00
delay_timer	Add a simple delay timer driver API	2015-06-17 13:13:54 +01:00
io	Remove direct usage of __attribute__((foo))	2016-01-14 10:55:17 -08:00
ti/uart	Driver for 16550 UART interface	2015-05-29 11:25:20 +05:30