Soby Mathew a91e12fbea Fix race in GIC IPRIORITY and ITARGET accessors ... GICD_IPRIORITYR and GICD_ITARGETSR specifically support byte addressing so that individual interrupt priorities can be atomically updated by issuing a single byte write. The previous implementation of gicd_set_ipriority() and gicd_set_itargetsr() used 32-bit register accesses, modifying values for 4 interrupts at a time, using a read-modify-write approach. This potentially may cause concurrent changes by other CPUs to the adjacent interrupts to be corrupted. This patch fixes the issue by modifying these accessors to use byte addressing. Fixes ARM-software/tf-issues#343 Change-Id: Iec28b5f5074045b00dfb8d5f5339b685f9425915		2016-02-09 16:50:36 +00:00
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common	Add ARM GICv3 driver without support for legacy operation	2015-11-26 12:29:48 +00:00
v2	Fix race in GIC IPRIORITY and ITARGET accessors	2016-02-09 16:50:36 +00:00
v3	Rename GICv3 interrupt group macros	2015-12-04 12:02:12 +00:00
arm_gic.c	Remove EL2/EL1 GICv3 register updates	2015-09-01 12:44:00 +01:00
gic_v2.c	Fix race in GIC IPRIORITY and ITARGET accessors	2016-02-09 16:50:36 +00:00
gic_v3.c	Reduce deep nesting of header files	2014-05-06 13:57:48 +01:00