Hadi Asyrafi fea24b88e4 intel: stratix10: Fix reliance on hard coded clock information ... Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03		2019-08-13 18:20:53 +08:00
..
s10_clock_manager.c	intel: stratix10: Fix reliance on hard coded clock information	2019-08-13 18:20:53 +08:00
s10_handoff.c	intel: Platform common code refactor	2019-08-07 12:19:11 +00:00
s10_mailbox.c	plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform	2019-02-26 09:25:14 +08:00
s10_memory_controller.c	plat: intel: Improve ECC scrubbing performance	2019-03-07 11:28:05 +08:00
s10_pinmux.c	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
s10_reset_manager.c	intel: Platform common code refactor	2019-08-07 12:19:11 +00:00
s10_system_manager.c	plat/intel: Fix SMPLSEL for MMC	2019-07-10 11:39:03 +08:00