Tejas Patel b6d7b3e9d6 plat: xilinx: versal: Add support to get clock rate value ... Add support to get clock's rate value. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I3ed881053ef323b2ca73e13edd0affda860d381d		2020-12-07 11:10:13 +00:00
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common	plat: xilinx: Mask unnecessary bytes of return error code	2020-12-07 11:08:09 +00:00
versal	plat: xilinx: versal: Add support to get clock rate value	2020-12-07 11:10:13 +00:00
zynqmp	plat: xilinx: zynqmp: Include GICv2 makefile	2020-12-03 20:30:37 -07:00