Tejas Patel b6d7b3e9d6 plat: xilinx: versal: Add support to get clock rate value ... Add support to get clock's rate value. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I3ed881053ef323b2ca73e13edd0affda860d381d		2020-12-07 11:10:13 +00:00
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aarch64	xilinx: versal: PLM to ATF handover	2020-01-23 03:01:22 -07:00
include	Create separate header for ARM specific SMCCC defines	2020-03-30 12:21:38 +00:00
pm_service	plat: xilinx: versal: Add support to get clock rate value	2020-12-07 11:10:13 +00:00
bl31_versal_setup.c	plat:xilinx:versal: Use defaults when PDI is without sw partitions	2020-12-07 11:09:47 +00:00
plat_psci.c	xilinx: versal: Skip store/restore of GIC during CPU idle	2020-12-07 11:07:41 +00:00
plat_topology.c	arm64: versal: Add support for new Xilinx Versal ACAPs	2018-11-09 15:06:53 +05:30
plat_versal.c	plat: xilinx: versal: Move versal_private.h to include directory	2020-01-15 11:01:28 -08:00
platform.mk	TF-A GICv3 driver: Introduce makefile	2020-03-30 10:54:01 +00:00
sip_svc_setup.c	xilinx: versal: enable ipi mailbox service	2020-01-15 11:02:37 -08:00
versal_gicv3.c	plat: xilinx: versal: Move versal_private.h to include directory	2020-01-15 11:01:28 -08:00
versal_ipi.c	xilinx: Add support to send PM API to PMC using IPI for versal	2020-01-15 11:01:37 -08:00