Tejas Patel b6d7b3e9d6 plat: xilinx: versal: Add support to get clock rate value ... Add support to get clock's rate value. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I3ed881053ef323b2ca73e13edd0affda860d381d		2020-12-07 11:10:13 +00:00
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pm_api_sys.c	plat: xilinx: versal: Add support to get clock rate value	2020-12-07 11:10:13 +00:00
pm_api_sys.h	plat: xilinx: versal: Add support to get clock rate value	2020-12-07 11:10:13 +00:00
pm_client.c	xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()	2020-12-07 11:07:24 +00:00
pm_defs.h	plat: xilinx: versal: Add support of set max latency for the device	2020-12-07 11:10:07 +00:00
pm_node.h	xilinx: Add support to send PM API to PMC using IPI for versal	2020-01-15 11:01:37 -08:00
pm_svc_main.c	plat: xilinx: versal: Add support to get clock rate value	2020-12-07 11:10:13 +00:00
pm_svc_main.h	xilinx: versal: Add SMC handler for EEMI API	2020-01-15 11:02:18 -08:00