b8fe48b6f2
Correct MCU clock parent selector: MCU subsystem clock is derived from clock PLL3_P, not PLL3. Correct AXI clock parent selector: AXI subsystem clock is derived from clock PLL2_P, not PLL2. This change also renames MCU clock and AXI clock resources to prevent confusion. Change-Id: If55618d180e7dce8e4f0977b0e586a6fa8ef28d1 Signed-off-by: Etienne Carriere <etienne.carriere@st.com> |
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|---|---|---|
| .. | ||
| bsec | ||
| clk | ||
| crypto | ||
| ddr | ||
| etzpc | ||
| fmc | ||
| gpio | ||
| i2c | ||
| io | ||
| iwdg | ||
| mmc | ||
| pmic | ||
| reset | ||
| spi | ||
| uart/aarch32 | ||