Varun Wadekar be87d920bf Tegra: memctrl_v2: implement MC txn override WAR ... This patch sets the Memory Controller's TXN_OVERRIDE registers for most write clients to CGID_ADR. This ensures ordering is maintained. In some cases WAW ordering problems could occur. There are different settings for Tegra version A01 v A02. Original changes by Alex Waterman <alexw@nvidia.com> Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2017-03-20 09:14:51 -07:00
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common	Tegra: memctrl_v2: implement MC txn override WAR	2017-03-20 09:14:51 -07:00
include	Tegra: memctrl_v2: implement MC txn override WAR	2017-03-20 09:14:51 -07:00
soc	Tegra: memctrl_v2: check GPU state before VPR programming	2017-03-20 09:14:39 -07:00
platform.mk	Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs	2017-03-07 10:27:21 -08:00