Varun Wadekar be87d920bf Tegra: memctrl_v2: implement MC txn override WAR ... This patch sets the Memory Controller's TXN_OVERRIDE registers for most write clients to CGID_ADR. This ensures ordering is maintained. In some cases WAW ordering problems could occur. There are different settings for Tegra version A01 v A02. Original changes by Alex Waterman <alexw@nvidia.com> Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2017-03-20 09:14:51 -07:00
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drivers	Tegra: memctrl_v2: implement MC txn override WAR	2017-03-20 09:14:51 -07:00
t132	Tegra: support for silicon/simulation platforms	2017-03-02 13:01:01 -08:00
t186	Tegra: memctrl_v2: implement MC txn override WAR	2017-03-20 09:14:51 -07:00
t210	Tegra: support for silicon/simulation platforms	2017-03-02 13:01:01 -08:00
plat_macros.S	Tegra: fix logic to calculate GICD_ISPENDR register address	2017-03-02 13:01:25 -08:00
platform_def.h	Tegra: increase ADDR_SPACE_SIZE to 35 bits	2017-03-02 13:02:27 -08:00
tegra_platform.h	Tegra: public interfaces to get the chip's major/minor versions	2017-03-20 08:54:16 -07:00
tegra_private.h	Tegra: get BL31 arguments from previous bootloader	2017-02-28 08:50:01 -08:00