Varun Wadekar be87d920bf Tegra: memctrl_v2: implement MC txn override WAR ... This patch sets the Memory Controller's TXN_OVERRIDE registers for most write clients to CGID_ADR. This ensures ordering is maintained. In some cases WAW ordering problems could occur. There are different settings for Tegra version A01 v A02. Original changes by Alex Waterman <alexw@nvidia.com> Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2017-03-20 09:14:51 -07:00
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arm	Add workaround for ARM Cortex-A53 erratum 855873	2017-03-20 10:57:46 +00:00
common	Merge pull request #861 from soby-mathew/sm/aarch32_fixes	2017-03-18 12:16:27 +00:00
compat	AArch32: Add essential ARM platform and FVP support	2016-08-10 18:01:38 +01:00
mediatek	plat/mediatek: Enable Cortex-A53 erratum 855873 workaround	2017-03-20 10:57:50 +00:00
nvidia/tegra	Tegra: memctrl_v2: implement MC txn override WAR	2017-03-20 09:14:51 -07:00
qemu	Replace some memset call by zeromem	2017-02-06 17:01:39 +00:00
rockchip	Merge pull request #854 from rockchip-linux/pm_plat	2017-03-03 23:29:01 +00:00
xilinx/zynqmp	Replace some memset call by zeromem	2017-02-06 17:01:39 +00:00