Lin Huang ca9286c68a rockchip: rk3399: improve the m0 enable flow ... This patch do following things: 1. Request hresetn_cm0s_pmu_req first then request poresetn_cm0s_pmu_req during M0 enable. 2. Do not diable M0 clock for ddr dvfs. 3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1 4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate to the M0 clock. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org>		2017-02-24 20:07:44 +08:00
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arm	Resolve build errors flagged by GCC 6.2	2017-01-26 13:47:37 +00:00
common	tbbr: Simplify conditional	2017-01-31 10:55:04 +00:00
compat	AArch32: Add essential ARM platform and FVP support	2016-08-10 18:01:38 +01:00
mediatek	Remove use of all deprecated APIs	2017-01-24 10:50:14 +08:00
nvidia/tegra	Use #ifdef for IMAGE_BL* instead of #if	2017-01-24 01:01:21 +09:00
qemu	Use #ifdef for IMAGE_BL* instead of #if	2017-01-24 01:01:21 +09:00
rockchip	rockchip: rk3399: improve the m0 enable flow	2017-02-24 20:07:44 +08:00
xilinx/zynqmp	Move BL_COHERENT_RAM_BASE/END defines to common_def.h	2017-01-18 19:33:41 +09:00