dp-arm d832aee900 aarch64: Enable Statistical Profiling Extensions for lower ELs ... SPE is only supported in non-secure state. Accesses to SPE specific registers from SEL1 will trap to EL3. During a world switch, before `TTBR` is modified the SPE profiling buffers are drained. This is to avoid a potential invalid memory access in SEL1. SPE is architecturally specified only for AArch64. Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>		2017-06-22 10:33:19 +01:00
..
aarch32	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
aarch64	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
compiler-rt	compiler-rt: Remove unused int_util.[ch] files	2017-05-24 15:39:28 +01:00
cpus	Unique names for defines in the CPU libraries	2017-06-14 15:00:13 -07:00
el3_runtime	aarch64: Enable Statistical Profiling Extensions for lower ELs	2017-06-22 10:33:19 +01:00
libfdt	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
locks	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
pmf	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
psci	Tegra: enable 'signed-comparison' compilation warning/errors	2017-06-14 14:59:07 -07:00
semihosting	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
stack_protector	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
stdlib	Simplify assert() to reduce memory usage	2017-05-16 09:58:08 +01:00
xlat_tables	Merge pull request #924 from antonio-nino-diaz-arm/an/fix-xn-bit	2017-05-05 09:50:34 +01:00
xlat_tables_v2	xlat_tables_v2: fix signed/unsigned comparisons	2017-06-20 14:39:34 +01:00