arm-trusted-firmware/plat/marvell/armada/a8k
Konstantin Porotchkin 109873cf4a plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows access to CP1/CP2 internal registers at
BLE stage if CP1/CP2 are connected.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
2021-02-25 09:59:17 +00:00
..
a70x0 plat: marvell: armada: add support for twin-die combined memory device 2020-07-30 15:15:40 +02:00
a70x0_amc plat: marvell: armada: add support for twin-die combined memory device 2020-07-30 15:15:40 +02:00
a80x0 plat/marvell: fix SPD handling in dram port 2021-02-11 09:43:18 +00:00
a80x0_mcbin plat/marvell: fix SPD handling in dram port 2021-02-11 09:43:18 +00:00
a80x0_puzzle plat/marvell: fix SPD handling in dram port 2021-02-11 09:43:18 +00:00
common plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage 2021-02-25 09:59:17 +00:00