109873cf4a
Map IO WIN to CP1 and CP2 at all stages including the BLE. Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly. This patch allows access to CP1/CP2 internal registers at BLE stage if CP1/CP2 are connected. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Yi Guo <yi.guo@cavium.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> |
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| .. | ||
| aarch64 | ||
| ble | ||
| include | ||
| mss | ||
| a8k_common.mk | ||
| plat_bl1_setup.c | ||
| plat_bl31_setup.c | ||
| plat_ble_setup.c | ||
| plat_pm.c | ||
| plat_pm_trace.c | ||
| plat_thermal.c | ||