Varun Wadekar 8061a973ec Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs ... A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to enable read/write access to the L2 and CPUECTRL registers. T210 is the only platform that needs to enable this config for now. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2015-07-17 19:06:54 +05:30
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aarch64	Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs	2015-07-17 19:06:54 +05:30
drivers	Tegra: PMC: lock SCRATCH22 register	2015-07-17 19:06:47 +05:30
tegra_bl31_setup.c	Tegra: introduce delay timer support	2015-07-17 19:06:36 +05:30
tegra_common.mk	Tegra: introduce delay timer support	2015-07-17 19:06:36 +05:30
tegra_delay_timer.c	Tegra: introduce delay timer support	2015-07-17 19:06:36 +05:30
tegra_gic.c	Add missing features to the Tegra GIC driver	2015-06-22 14:55:49 +05:30
tegra_pm.c	Implement get_sys_suspend_power_state() handler for Tegra	2015-07-06 09:15:02 +05:30
tegra_sip_calls.c	Reserve a Video Memory aperture in DRAM memory	2015-06-12 17:40:31 +05:30
tegra_topology.c	Support for NVIDIA's Tegra T210 SoCs	2015-05-29 16:43:25 +05:30