2015-03-19 18:58:55 +00:00
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/*
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2020-01-24 13:30:28 +00:00
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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2015-03-19 18:58:55 +00:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2015-03-19 18:58:55 +00:00
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*/
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2018-12-14 00:18:21 +00:00
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#include <assert.h>
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#include <platform_def.h>
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2015-03-19 18:58:55 +00:00
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#include <arch.h>
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#include <arch_helpers.h>
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2018-12-14 00:18:21 +00:00
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#include <common/debug.h>
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#include <common/romlib.h>
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#include <lib/mmio.h>
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2020-07-24 03:26:05 +01:00
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#include <lib/smccc.h>
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2018-12-14 00:18:21 +00:00
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#include <lib/xlat_tables/xlat_tables_compat.h>
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2020-07-24 03:26:05 +01:00
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#include <services/arm_arch_svc.h>
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2019-01-25 14:30:04 +00:00
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#include <plat/arm/common/plat_arm.h>
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2018-12-14 00:18:21 +00:00
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#include <plat/common/platform.h>
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2015-03-19 18:58:55 +00:00
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak plat_get_ns_image_entrypoint
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2015-11-12 18:52:34 +00:00
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#pragma weak plat_arm_get_mmap
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2016-05-19 10:00:28 +01:00
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/* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
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* conflicts with the definition in plat/common. */
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#pragma weak plat_get_syscnt_freq2
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2015-03-19 18:58:55 +00:00
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2020-02-22 08:43:00 +00:00
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/* Get ARM SOC-ID */
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#pragma weak plat_arm_get_soc_id
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2019-11-07 15:18:03 +00:00
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/*******************************************************************************
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* Changes the memory attributes for the region of mapped memory where the BL
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* image's translation tables are located such that the tables will have
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* read-only permissions.
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******************************************************************************/
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#if PLAT_RO_XLAT_TABLES
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void arm_xlat_make_tables_readonly(void)
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{
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int rc = xlat_make_tables_readonly();
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if (rc != 0) {
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ERROR("Failed to make translation tables read-only at EL%u.\n",
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get_current_el());
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panic();
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}
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INFO("Translation tables are now read-only at EL%u.\n",
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get_current_el());
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}
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#endif
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2018-05-23 09:27:06 +01:00
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void arm_setup_romlib(void)
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{
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#if USE_ROMLIB
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if (!rom_lib_init(ROMLIB_VERSION))
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panic();
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#endif
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}
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2016-03-23 10:11:10 +00:00
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uintptr_t plat_get_ns_image_entrypoint(void)
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2015-03-19 18:58:55 +00:00
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{
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2016-05-09 17:20:10 +01:00
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#ifdef PRELOADED_BL33_BASE
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return PRELOADED_BL33_BASE;
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#else
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2019-01-31 14:01:32 +00:00
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return PLAT_ARM_NS_IMAGE_BASE;
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2016-05-09 17:20:10 +01:00
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#endif
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2015-03-19 18:58:55 +00:00
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}
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/*******************************************************************************
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* Gets SPSR for BL32 entry
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******************************************************************************/
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uint32_t arm_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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2015-12-14 09:35:25 +00:00
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* setting the SPSR prior to entry into the BL32 image.
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2015-03-19 18:58:55 +00:00
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*/
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return 0;
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}
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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2019-07-09 22:02:43 +01:00
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#ifdef __aarch64__
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2015-03-19 18:58:55 +00:00
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uint32_t arm_get_spsr_for_bl33_entry(void)
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{
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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2018-10-31 15:25:35 +00:00
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mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
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2015-03-19 18:58:55 +00:00
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-04 22:18:52 +01:00
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spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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2015-03-19 18:58:55 +00:00
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return spsr;
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}
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2016-07-11 14:13:56 +01:00
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#else
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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uint32_t arm_get_spsr_for_bl33_entry(void)
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{
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unsigned int hyp_status, mode, spsr;
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hyp_status = GET_VIRT_EXT(read_id_pfr1());
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mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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2019-07-09 22:02:43 +01:00
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#endif /* __aarch64__ */
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2015-03-19 18:58:55 +00:00
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2015-10-12 17:32:29 +01:00
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/*******************************************************************************
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* Configures access to the system counter timer module.
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******************************************************************************/
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2016-03-07 04:23:39 +00:00
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#ifdef ARM_SYS_TIMCTL_BASE
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2015-10-12 17:32:29 +01:00
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void arm_configure_sys_timer(void)
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{
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unsigned int reg_val;
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2018-06-11 16:21:30 +01:00
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/* Read the frequency of the system counter */
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unsigned int freq_val = plat_get_syscnt_freq2();
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2015-11-06 16:02:32 +00:00
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#if ARM_CONFIG_CNTACR
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2018-11-06 13:14:21 +00:00
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reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT);
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reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT);
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reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT);
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2015-10-12 17:32:29 +01:00
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mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
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2015-11-06 16:02:32 +00:00
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#endif /* ARM_CONFIG_CNTACR */
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2015-10-12 17:32:29 +01:00
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2018-11-06 13:14:21 +00:00
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reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
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2015-10-12 17:32:29 +01:00
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mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
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2018-06-11 16:21:30 +01:00
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/*
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* Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ
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* system register initialized during psci_arch_setup() is different
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* from this and has to be updated independently.
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*/
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mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
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2019-05-10 08:52:07 +01:00
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#if defined(PLAT_juno) || defined(PLAT_n1sdp)
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2018-06-11 16:21:30 +01:00
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/*
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* Initialize CNTFRQ register in Non-secure CNTBase frame.
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2019-05-10 08:52:07 +01:00
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* This is only required for Juno and N1SDP, because they do not
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* follow ARM ARM in that the value updated in CNTFRQ is not
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* reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
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2018-06-11 16:21:30 +01:00
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*/
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2018-11-22 15:53:17 +00:00
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mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val);
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2018-06-11 16:21:30 +01:00
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#endif
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2015-10-12 17:32:29 +01:00
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}
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2016-03-07 04:23:39 +00:00
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#endif /* ARM_SYS_TIMCTL_BASE */
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2015-11-12 18:52:34 +00:00
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/*******************************************************************************
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* Returns ARM platform specific memory map regions.
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******************************************************************************/
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const mmap_region_t *plat_arm_get_mmap(void)
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{
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return plat_arm_mmap;
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}
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2016-04-14 14:49:37 +01:00
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2016-04-26 10:36:29 +01:00
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#ifdef ARM_SYS_CNTCTL_BASE
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2016-05-19 10:00:28 +01:00
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unsigned int plat_get_syscnt_freq2(void)
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{
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2016-06-03 15:00:46 +01:00
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unsigned int counter_base_frequency;
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2016-04-14 14:49:37 +01:00
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/* Read the frequency from Frequency modes table */
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counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
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/* The first entry of the frequency modes table must not be 0 */
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2018-11-06 13:14:21 +00:00
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if (counter_base_frequency == 0U)
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2016-04-14 14:49:37 +01:00
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panic();
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return counter_base_frequency;
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}
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2016-05-19 10:00:28 +01:00
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2016-04-26 10:36:29 +01:00
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#endif /* ARM_SYS_CNTCTL_BASE */
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2017-10-19 09:15:15 +01:00
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#if SDEI_SUPPORT
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/*
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* Translate SDEI entry point to PA, and perform standard ARM entry point
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* validation on it.
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*/
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int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode)
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{
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uint64_t par, pa;
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2020-01-24 13:30:28 +00:00
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u_register_t scr_el3;
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2017-10-19 09:15:15 +01:00
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/* Doing Non-secure address translation requires SCR_EL3.NS set */
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scr_el3 = read_scr_el3();
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write_scr_el3(scr_el3 | SCR_NS_BIT);
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isb();
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assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1));
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if (client_mode == MODE_EL2) {
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/*
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* Translate entry point to Physical Address using the EL2
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* translation regime.
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*/
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ats1e2r(ep);
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} else {
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/*
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* Translate entry point to Physical Address using the EL1&0
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* translation regime, including stage 2.
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*/
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2020-07-14 14:43:12 +01:00
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AT(ats12e1r, ep);
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2017-10-19 09:15:15 +01:00
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}
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isb();
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par = read_par_el1();
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/* Restore original SCRL_EL3 */
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write_scr_el3(scr_el3);
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isb();
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/* If the translation resulted in fault, return failure */
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if ((par & PAR_F_MASK) != 0)
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return -1;
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/* Extract Physical Address from PAR */
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pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT));
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/* Perform NS entry point validation on the physical address */
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return arm_validate_ns_entrypoint(pa);
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}
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#endif
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2020-02-22 08:43:00 +00:00
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