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arm-trusted-firmware/plat/arm/board/arm_fpga/include/platform_def.h

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plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
2019-11-11 11:11:06 +00:00
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <arch.h>
plat/arm/board/arm_fpga: Enable position-independent execution This allows the BL31 port to run with position-independent execution enabled so that it can be ran from any address in the system. This increases the flexibility of the image, allowing it to be ran from other locations rather than only its hardcoded absolute address (currently set to the typical DRAM base of 2GB). This may be useful for future images that describe system configurations with other memory layouts (e.g. where SRAM is included). It does this by setting ENABLE_PIE=1 and changing the absolute address to 0. The load address of bl31.bin can then be specified by the -l [load address] argument in the fpga-run command (additionally, this address is required by any preceding payloads that specify the start address. For ELF payloads this is usually extracted automatically by reading the entrypoint address in the header, however bl31.bin is a different file format so has this additional dependency). Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143
2020-01-07 14:43:01 +00:00
#include <plat/common/common_def.h>
#include <platform_def.h>
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
2019-11-11 11:11:06 +00:00
#include "../fpga_def.h"
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
#define PLATFORM_STACK_SIZE UL(0x800)
#define CACHE_WRITEBACK_SHIFT U(6)
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
arm_fpga: Add support for topology self-discovery As secondary cores show up, they populate an array to announce themselves so plat_core_pos_by_mpidr() can return an invalid COREID code for any non-existing MPIDR that it is queried about. The Power Domain Tree Description is populated with a topology based on the maximum harcoded values. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I8fd64761a2296714ce0f37c46544f3e6f13b5f61
2020-05-13 14:09:58 +01:00
#define PLATFORM_CORE_COUNT \
(FPGA_MAX_CLUSTER_COUNT * \
FPGA_MAX_CPUS_PER_CLUSTER * \
FPGA_MAX_PE_PER_CPU)
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
2019-11-11 11:11:06 +00:00
arm_fpga: Add support for topology self-discovery As secondary cores show up, they populate an array to announce themselves so plat_core_pos_by_mpidr() can return an invalid COREID code for any non-existing MPIDR that it is queried about. The Power Domain Tree Description is populated with a topology based on the maximum harcoded values. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I8fd64761a2296714ce0f37c46544f3e6f13b5f61
2020-05-13 14:09:58 +01:00
#define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + PLATFORM_CORE_COUNT + 1)
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
2019-11-11 11:11:06 +00:00
plat/arm/board/arm_fpga: Enable position-independent execution This allows the BL31 port to run with position-independent execution enabled so that it can be ran from any address in the system. This increases the flexibility of the image, allowing it to be ran from other locations rather than only its hardcoded absolute address (currently set to the typical DRAM base of 2GB). This may be useful for future images that describe system configurations with other memory layouts (e.g. where SRAM is included). It does this by setting ENABLE_PIE=1 and changing the absolute address to 0. The load address of bl31.bin can then be specified by the -l [load address] argument in the fpga-run command (additionally, this address is required by any preceding payloads that specify the start address. For ELF payloads this is usually extracted automatically by reading the entrypoint address in the header, however bl31.bin is a different file format so has this additional dependency). Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143
2020-01-07 14:43:01 +00:00
#if !ENABLE_PIE
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
2019-11-11 11:11:06 +00:00
#define BL31_BASE UL(0x80000000)
fix(arm_fpga): limit BL31 memory usage At the moment we specified the BL31 memory limits to 1MB; since we typically have gigabytes of DRAM, we can be quite generous. However the default parameters expect the devicetree binary at 0x80070000, so we should actually make sure we have no code or data beyond that point. Limit the ARM FPGA BL31 memory footprint to this available 7*64K region. We stay within the limit at the moment, with more than half of it reserved for stacks, so this could be downsized later should we run into problems. The PIE addresses stay as they are, since the default addresses do not apply there anywhere, and the build is broken anyway. Change-Id: I7768af1a93ff67096f4359fc5f5feb66464bafaa Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-02 17:02:24 +01:00
#define BL31_LIMIT UL(0x80070000)
plat/arm/board/arm_fpga: Enable position-independent execution This allows the BL31 port to run with position-independent execution enabled so that it can be ran from any address in the system. This increases the flexibility of the image, allowing it to be ran from other locations rather than only its hardcoded absolute address (currently set to the typical DRAM base of 2GB). This may be useful for future images that describe system configurations with other memory layouts (e.g. where SRAM is included). It does this by setting ENABLE_PIE=1 and changing the absolute address to 0. The load address of bl31.bin can then be specified by the -l [load address] argument in the fpga-run command (additionally, this address is required by any preceding payloads that specify the start address. For ELF payloads this is usually extracted automatically by reading the entrypoint address in the header, however bl31.bin is a different file format so has this additional dependency). Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143
2020-01-07 14:43:01 +00:00
#else
#define BL31_BASE UL(0x0)
#define BL31_LIMIT UL(0x01000000)
#endif
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
2019-11-11 11:11:06 +00:00
plat/arm/board/arm_fpga: Initialize the Generic Interrupt Controller This initializes the GIC using the Arm GIC drivers in TF-A. The initial FPGA image uses a GIC600 implementation, and so that its power controller is enabled, this platform port calls the corresponding implementation-specific routines. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I88d5a073eead4b653b1ca73273182cd98a95e4c5
2019-12-03 14:08:21 +00:00
#define PLAT_SDEI_NORMAL_PRI 0x70
#define ARM_IRQ_SEC_PHY_TIMER 29
#define ARM_IRQ_SEC_SGI_0 8
#define ARM_IRQ_SEC_SGI_1 9
#define ARM_IRQ_SEC_SGI_2 10
#define ARM_IRQ_SEC_SGI_3 11
#define ARM_IRQ_SEC_SGI_4 12
#define ARM_IRQ_SEC_SGI_5 13
#define ARM_IRQ_SEC_SGI_6 14
#define ARM_IRQ_SEC_SGI_7 15
/*
* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
#define PLATFORM_G1S_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE)
#define PLATFORM_G0_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE)
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE 2
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
2019-11-11 11:11:06 +00:00
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
plat/arm/board/arm_fpga: Add PSCI implementation for FPGA images This adds a basic PSCI implementation allow secondary CPUs to be released from an initial state and continue through to the warm boot entrypoint. Each secondary CPU is kept in a holding pen, whereby it polls the value representing its hold state, by reading this from an array that acts as a table for all the PEs. The hold states are initially set to 0 for all cores to indicate that the executing core should continue polling. To prevent the secondary CPUs from interfering with the platform's initialization, they are only updated by the primary CPU once the cold boot sequence has completed and fpga_pwr_domain_on(mpidr) is called. The polling target CPU will then read 1 (which indicates that it should branch to the warm reset entrypoint) and then jump to that address rather than continue polling. In addition to the initial polling behaviour of the secondary CPUs before their warm boot reset sequence, they are also placed in a low-power wfe() state at the end of each poll; accordingly, the PSCI fpga_pwr_domain_on(mpidr) function also signals an event to all cores (after updating the target CPU's hold entry) to wake them from this state, allowing any secondary CPUs that are still polling to check their hold state again. This method is in accordance with both the PSCI and Linux kernel recommendations, as the lessened overhead reduces the energy consumption associated with the busy-loop. The table of hold entries is implemented by a global array as shared SRAM (which is used by other platforms in similar implementations) is not available on the FPGA images. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I65cfd1892f8be1dfcb285f0e1e94e7a9870cdf5a
2019-12-02 13:21:52 +00:00
#define PLAT_FPGA_HOLD_ENTRY_SHIFT 3
#define PLAT_FPGA_HOLD_STATE_WAIT 0
#define PLAT_FPGA_HOLD_STATE_GO 1
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
2019-11-11 11:11:06 +00:00
#endif