2013-10-25 09:08:21 +01:00
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/*
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2016-02-15 11:54:14 +00:00
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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2013-10-25 09:08:21 +01:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2013-10-25 09:08:21 +01:00
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*/
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2015-03-19 19:17:53 +00:00
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#include <plat_arm.h>
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2014-05-14 17:44:19 +01:00
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#include "fvp_private.h"
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2013-10-25 09:08:21 +01:00
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2016-09-13 17:07:57 +01:00
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#if LOAD_IMAGE_V2
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void bl31_early_platform_setup(void *from_bl2,
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void *plat_params_from_bl2)
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#else
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2014-04-15 18:08:08 +01:00
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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2014-05-16 18:48:12 +01:00
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void *plat_params_from_bl2)
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2016-09-13 17:07:57 +01:00
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#endif
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2013-10-25 09:08:21 +01:00
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{
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2015-03-19 19:17:53 +00:00
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arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);
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2014-03-27 14:33:15 +00:00
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2013-10-25 09:08:21 +01:00
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/* Initialize the platform config for future decision making */
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2014-05-15 14:53:30 +01:00
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fvp_config_setup();
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2014-04-24 11:02:16 +01:00
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2013-10-25 09:08:21 +01:00
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/*
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2016-02-15 11:54:14 +00:00
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* Initialize the correct interconnect for this cluster during cold
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* boot. No need for locks as no other CPU is active.
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2013-10-25 09:08:21 +01:00
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*/
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2016-02-15 11:54:14 +00:00
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fvp_interconnect_init();
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2015-05-14 14:13:05 +01:00
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2015-03-19 19:17:53 +00:00
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/*
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2016-02-15 11:54:14 +00:00
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* Enable coherency in interconnect for the primary CPU's cluster.
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2015-05-14 14:13:05 +01:00
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* Earlier bootloader stages might already do this (e.g. Trusted
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* Firmware's BL1 does it) but we can't assume so. There is no harm in
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* executing this code twice anyway.
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2015-03-19 19:17:53 +00:00
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* FVP PSCI code will enable coherency for other clusters.
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*/
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2016-02-15 11:54:14 +00:00
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fvp_interconnect_enable();
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2013-10-25 09:08:21 +01:00
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}
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